final_04_sol

final_04_sol - 04-1 04-2 04-3 2004 ELEC151 — Final...

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Unformatted text preview: 04-1 04-2 04-3 2004 ELEC151 — Final Examination (6 Questions and 2 Pages, Open Note of One A4 Sheet) (Answer only on two sides of the answer booklet) Name and §tudent Number Write down your name and student number an the answer booklet. Design Process - A Seguence Detector (20%) Design a sequence detector which investigates an input sequence X and produces an output 2 = 1 WHENEVER the input sequence of "0010' has been seen. Use T flip-flop for the Q1 state register and J-K flip-flop for the 00 state register, and Gray code assignment to implement the detector in Mealy machine and show a) Minimized state diagram (5%) b) Minimized next-state and output logic functions in 2—level Boolean expressions (5%) c) Write a VHDL code to design a TFF with T input, rising-edge CLK input and an active-low synchronous RESET input (10%) Design Process - A Seguential Circuit (15%) A sequential circuit has three state registers (A B C), one input X and one output 2, as illustrated in the following state diagram. Use T flip-flop for A state register, D flip- flop for B state register and J-K flip-flop for C state register to implement this sequential circuit. Show the minimized next-state and output logic functions in 2— level Boolean expressions and calculate for their total equivalent gate counts if all the combinational logic is implemented by NAND gates. VHDL Synthesis — A Vending Machine (20%) A vending machine delivers a package of gum after 20 cents are deposited. The machine has single coin slot for nickels (5 cents) or dimes (10 cents). The machine can not make change. But if more than 20 cents are deposited, it will credit the buyer the balance for a second purchase. a) Draw a minimized state transition diagram in Mealy machine. (5%) b) Write a VHDL code to synthesize this vending machine. (15%) ELECiSi Final Exam. 16-Dec-2004. 1/2 04-4 04-5. 04-6. Design with SPLD (15%) Design with one SPLD for the following four Boolean functions W(A,B,C) = 2(1,2,4,6) X(A.B,C) = 2(0,3,5,6) Y(A,B,C) = 2(2,6) ZiA,B,C) = E(1,2,3,5,7) a) What is the smallest PROM required for this design? (5%) (PROM is expressed in terms of 2n (word size) x m (bit size). Simply write .. down the smallest values of 2n and m) b) Minimize the number of product terms for a PLA implementation. Write down these product terms? (5%) c) What is the minimal number of OR gates of a PAL required for this design? Each OR gate of the PAL is connected to 3 AND gates. (5%) State Reduction (15%) Given a state transition diagram below, use implication chart to determine and draw the fully reduced state transition diagram. Present Next State State X=0 X=1 X=0 ll .4 IommUOm> U>ImmmIO mIUOI>0m Aouoovox Reverse En ineerin -S nchronous Lo lo (15%) Given a Mealy machine below, draw its complete state transition diagram. Note that the states are represented by (QA QB QC). ELEC151 Final Exam. 16-Dec-2004, 2/2 o4—\ SEQUENCE Derccratz 04,} A $3,90ng (,‘Rcm : :0 0:” $340 @ (akmwve Assléwmfi‘: ('0 00,9 Ir ' XKKKXfi—— _oo—OQO_ KKKXKX—OQ~QOO_O_ XKAKKKXX-oxx_oxx C) LIBRARY ieee ; USE ieea . std_1oqic_1164 . all ; —-- 04-1C A TFF with synchronous RESET I ' TA: A+ B'x 3C: AH-A‘BX ENTITY tff IS ‘ I pox-r (1', cm, RESET: IN s'rn__1.ocxc; Q: our STD_LOGIC); --(or: 1(a)“! undClK‘tVEflT) END tiff; \LDO ARCHITECTURE behavioral or ctr Is :Do~ — BEGIN PROCESS '1‘ cm: RESET ( I I ) 2 BEGIN IF rising_edge (CLK) THEN IF RESETI‘O' THEN Q <= 0; WI“ €fl0/‘3 . ELSE b0. Q <- QWEEN '1'=‘0'; Y- X 9 <= NOT 0 WHEN Twp; 0.; (65$; END IF; END IF} END PROCESS; END behavioral; ZHH 35 +15 + 0.: = “‘5 3:02}; /0.S‘+a 13'9a1es:@ 0759ch A 04-4 Begum) \mn 4PM) LIBRARY ieee; --- 04—3 A Vending Machine M USE ieee . Itd_1ogic_1164 .ell; ENTITY vendingJMchine IS 3 Wok 4 PORT (CLK, N, D: IN STD_IDGIC; OPEN: OUT STD_IDGIC; 9: our sm_mc:c_vzc'ron (1 dawnto 0)); 23 X 4. P96 M @ END vending fichine; ARCHITECTURE behavioral OP vending_mchine IS TYPE stete_type IS (zero, five, ten, fifteen); @ SIGNAL PS: state_type; BEGIN transition: PROCESS (CLK, PS. N, D) -- State transitions BEGIN IF rising~edge (CLK) TEEN CASE PS IS WHEN zero -> IF N-‘l' TEEN PS <- five; ELSEIP Da‘l' TEEN PS <- ten; ELSE PS < zero; ENDIP; WHEN five I) IF N=‘1' TEEN PS <I ten; ELSEIF D=‘1' THEN PS <- fifteen; ELSE PS < five; ENDIP'; WHEN ten => IF N=‘1’ TEEN PS <- fifteen; ELSEIF D=‘1’ TEEN PS <- zero; ELSE PS < ten; ENDIP'; WHEN fifteen => IF N=‘1' THEN PS <= zero; ELSEIF D=‘1' THEN PS <- five; ELSE PS < fifteen; D/1 Nl1 ENDIP; END CASE END IF END PROCESS transition; W: Ac‘+BC+ A'EJC \/ wt. Au Esc + A'6’c' D'N'IO X = A'B‘C' + A'Bc + mad 4 Age X'= A'6'C + A'Bc' + ABC + Aa‘c’ V 1 gull Y = BC' v a Y'= B'+C “BEE Z s A'ngc 'II 2' v Ad-I 6’6} V semq W I X. ,Y “Mal 2' -§wmifms ‘ 31m OLUL 7 P/Lodué'i MM, ‘ l1 D'N'IO gum: PROCESS (PS, N, D) -- Output of Neely Machine BEGIN CASE PS IS WHEN zero -> OPEN <= ‘0'; WHEN five => OPEN <= ‘0'; WHEN ten => IF D=‘1’ TEEN OPEN <- ‘1'; ELSE OPEN <= ‘0'; ENDIF; WHEN fifteen -> IF N=‘1' OR na‘1' THEN OPEN <- ‘1'; ELSE OPEN <= ‘0'; Ac' ) Bc' A'E'c , A'sc', ARC, Ag'c' ,B'C' D m elm/‘3‘ ENDIF; END PSCDEscsAsfum; c) W, Y Who‘ 2 «EtmziCm 0.96; 1 OR suit WITH PS SELECT -- State Assignment Q <- “00" WHEN zero; ‘01” WfiEN five; “10" WHEN ten; .15" WHEN fifteen; $ 5 012 8412.9 END behaviroal; y I‘M/warm usu, 2 (>2 3dr. A. K A. arm yxffiU IX X .+ 45% (WK +( 6+: MK X wAc +A a .YW...K \FL + a B A o- L' I \ VA TWP )+.+'C M6;%:MIXV_A+ WT “TA m” .eM/Ax A @kJIJA flwAA ____= = Q :5 N IT AC. ,0 mi; we 0 hn u orrnt‘ M \ m x 4m \ aw» em 1H. m WW. 6 n. w M mm mm. b. w «W T EH é WM K) 2'» «I ...
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This note was uploaded on 09/16/2010 for the course ELEC 151 taught by Professor Cy during the Spring '10 term at HKUST.

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final_04_sol - 04-1 04-2 04-3 2004 ELEC151 — Final...

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