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final_05_sol

# final_05_sol - 0 05-1 05-2 05-3 2005 ELEC151 —— Final...

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Unformatted text preview: 0. 05-1 05-2 05-3 2005 ELEC151 —— Final Examination (6 Questions and 2 Pages, Open Note of One A4 Sheet, Two Sides) (Answer only on two sides of the answer booklet) Name and Student Number Write down your name and student number on the answer booklet. Design Process — A Seguence Detector (20%) Design a sequence detector which investigates an input sequence X and produces an output 2 = 1 WHENEVER the input sequence of '010' or “100" has been seen. Use D flip-flop for the 02 state register, T flip-flop for the Qt state register and J-K flip-flop for the 00 state register, and binary assignment to implement this Sequence detector in Mealy machine and show a) Minimized state diagram (10%) b) Minimized next-state and output logic functions in 2-level Boolean expressions (10%) (Use (02 Q1 00) to represent states) Design Process — A Binam UgIDown Counter (15%) We have studied a binary up/down counter in the textbook, and equivalent Tl'L lC 74L8190/191 in the lecture note. In this question, please design a 2-bit binary up/down counter, which has two inputs E and M. When E=0, the counter is disabled and remains in the same state or output. When E=1 and, M=0, the counter counts down from 00 to 11 to 10 to 01 back to 00 and repeats. When E=1 and M=1, the counter counts up from 00 to O1 to 10 to 11 back to 00 and repeats. Use T flip-flop for Q1 and JK flip-flop for 00 for this design and show. a) Minimized state diagram (5%) b) Minimized next-state logic functions in 2-level Boolean expressions and their equivalent gate counts (10%) VHDL Synthesis — A Seguential Circuit (20%) A sequential circuit has three state registers, one input X and one output 2. as illustrated in the following state diagram. Write a VHDL code to synthesize this sequential circuit. (Write only the ENTITY and ARCHITECTURE blocks) ELEC151 Final Exam. 12-Dec-2005, 1/2 05-4 05-5. 05-6. Design with SPLD (15%) Design with one SPLD for the following four Boolean functions W(A.B,C) = 2(013l5l7), X(A.B.C) = 23(2.3,4.5) Y(A,B,C) = 2(01113141517) Z(AIBIC) = 2(01416) a) What is the smallest PROM required for this design? (5%) (PROM is expressed in terms of 2n (word size) x m (bit size). Simply write down the smallest values of 2” and m) b) Minimize the number of product terms for a PLA implementation. Write down these produ'ct terms? (5%) c) What is the minimal number of OR gates of a PAL required for this design? Each OR gate of the PAL is connected to 3 AND gates. (5%) W (15%) Given a state transition diagram below, use implication chart to determine and draw the fully reduced state transition diagram. 1/0 ( tWV’WR /0 0,; 10,0 0/0 ® Um Reverse En ineerin -S nchronous Lo ic (15%) Draw the complete state transition diagram for a Mealy machine shown below. Note that the states are represented by (GA QB QC). ELEC151 Final Exam. 12-Dec-2005, 2/2 "'09. QengL-Ze “we wamwzs km) 93.0% «we «Mes 6», Meme Madam lo) gunmen 41M? Tnmsmw Tug: * ey.*_9:_:2__-__ 9.2."- o \ o o O o O l o \ O O \ o 0 0 \ \ \ O o o o ( o a \ 0 l o O 0 I I o 0 o o o \ g, THE GATE Comm \9 LSX1~H +0.5 -: ‘? 4-4) :3, Mgvxﬁg W6 4 WWW“ ' W \N'; AL4‘EC4—Ng‘d \N‘c ALU Qc'kA'éC v )( -: Aﬁ\+P\‘B \/' )6: A‘QW-AB Y: rah-C ‘(15 BC‘ \/ 1 | H'o l . Z= AHB'C AND 3— 0 2‘: A'mc v gELGCY W‘1X ,Y‘ Omol 2‘ «ﬁx/“chad 26c! 6 Produci'wm. ' ' :1 v I w AC' gc'Agé'Ag ”a”; ,[email protected]_ \$9,053 PORT ( CLK, x: IN STD_LOGIC; I: OUT STD_LOGIC; TA: A. (8'+¥) : AB! 'fAX . J ' M E Q: om- STD_LOGIC_VECTOR (.2 downto 0)); | I . l 5’“; DB: A'(C'+X’)‘ (Bi-(ids) : ABQA’ACX‘FABXTACK ARCHITECTURE behavioral OF fsm IS > s a e e a, , c, d, 6 ; ya = (AH). (WW ) t MW. + M + 8.x “mm?” b ’ }. BEGIN ,6. READ THE; NEXT. STATE Loam, , I ENTITY fsm IS ——— 05-3 A Sequential circuit .3 [(0 e x ‘ transit: PROCESS (cm, PS, x) -— State Transitions BEGIN . z _—_ Al + X IF rising_edge (CLK) THEN CASE ps IS WHEN a => IF X=‘0’ THEN PS <= d; E A+=(AB'+AX)~A'+ (AE‘MNA -_— Agx’ : _, 3553“» + ~ ' ‘ ' . ‘ "m =’ m" PS B, — . ABC 4 ACK + ABX + AcX .. mm . .+ I I \ , l I W C => IF x=‘o_' 'EHEN PS <= c; C. : (AB+AX“AX+BXB'C 4’ XC :' :ISEFES <— a, = AB’L' + Ac'x' +A‘c‘ X + 8' c')! + 6x." m d =, 35:12:??? PS b; (XE A9 WHEN e => 5:313:20! THEN rs <= c; {0 co (>1 ELSE ps <= d; ENDIF; END CASE END IF END PROCESS transition; anyname: PROCESS (PS) -— Output of Mealy Machine BEGIN CASE PS IS WHEN a => IF x=‘o' THEN 2 <= ‘0'; ENDIF; WHEN b => IF x=‘o' THEN 2 <= ‘0'; ENDIF; WHEN c => IF x=‘o' THEN Z <= ‘0’; ENDIF; WHEN d => IF x=‘o' THEN 2 <= ‘0'; ENDIF; WHEN a => IF x=‘o' THEN Z <= ‘0'; ENDIF; END CASE END PROCESS anyname; WITH PS SELECT -- State Assignment Q <= “000" WHEN a; “001” WHEN I); “010" WHEN C; “011" WHEN (I; “100” WHEN 9; END behaviroal; ...
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final_05_sol - 0 05-1 05-2 05-3 2005 ELEC151 —— Final...

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