CS530-Fall2010-HW2

CS530-Fall2010-HW2 - CS 530, Fall 2010 Computer...

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CS 530, Fall 2010 Computer Architecture Homework #2 Due Date: 9 Sep 2010 1. In this problem, we examine how resource hazards, control hazards and ISA design can affect pipelined execution. Consider the following fragment of MIPS code: lw $1, 40($6) beq $2,$0, Label ; Assume $2 -- $0 sw $6, 50($2) Label: add $2, $3, $4 sw $3,50($4) a. Assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we have only one memory (for both instructions and data), there is a structural hazard every time we need to fetch an instruction in the same cycle in which another instruction accesses data. To guarantee forward progress, this hazard must always be resolved in favor of the instruction that accesses data. What is the total execution time of this instruction sequence in the five- stage pipeline that only has one memory? We have seen that data hazards can be eliminated by adding nops to the code. Can you do the same with this structural hazard? Why?
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CS530-Fall2010-HW2 - CS 530, Fall 2010 Computer...

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