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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-15, NO. 6, DECEMBER 1980 A High Performance Low Power Filter 929 CMOS Channel WILLIAM C. BLACK, JR., MEMBER, IEEE, DAVID J. ALLSTOT, MEMBER,IEEE, AND RAY A. REED, MEMBER, IEEE Abstract-A new CMOS PCM channel fiiter is described, which includes transmit and receive filters on a single die. This chip displays an idle-channel noise of typically O dBrnCO, a POWeI supply rejection ratio of 40-50 dB at 1 kHz, and a fully operational power dissipation of only 35 mW, making it very cost effective in telecommunication switching systems. The design of this chip, including architectural, switched capacitor filter, and amplifier considerations is described, and typical experimental results are presented. I. INTRODUCTION P ULSE-CODE-MODULATION (PCM) techniques have become quite common in telephone switching and trans- mission systems, and are ahnost universally employed in new systems. In these techniques, the analog subscriber lines are connected with the digitrd switching network by way of a subscriber-line unit, which performs all necessary interface and conversion functions. Typically, this line unit contains a 2/4 tire interface circuit, three precision fiiters (line-frequency reject, anti-aliasing, and output smoothing fiiters), and a Codec circuit, which performs channel encoding and decoding at an 8 kHz rate. As circuitry to perform these functions must exist for each subscriber line, a significant portion of the total switching sys- tem cost rests in each component of the line unit. Years of effort in the area of monolithic A/D and D/A conversion tech- niques have succeeded in reducing the Codec to a fairly cost- effective integrated form [1] - [4], although attempts to inte- grate the fiiter and line-interface functions have, in general, proven less successful. Recently, switched capacitor tech- niques have offered the potential of very low-cost fiiters [5]. Many of these techniques have been employed in monolithic channel bank falters, which have often met the required fre- quency response characteristics [6], [7]. Monolithic realiza- tions to date, however, have suffered from high-noise output, lower power supply rejection, and high-power dissipation, which have severely degraded the cost-effectiveness of these falters in switching systems. In the device presented here, a number of new circuit tech- niques are used to provide improved performance over past monolithic implementations, and which, in fact, provides Manuscript received April 28, 1980; revised August 15, 1980. W. C. Black, Jr. is with the Electronics Research Laboratory, Uni- versity of California, Berkeley, CA 94720. D. J. Ellstot was with the Electronics Research Laboratory, Univer- sity of California, Berkeley, CA 94720. He is now with MOSTEK, Inc., CsrrolIton, TX 75006. R. A. Reed is with NationaJ Semiconductor Corporation, Santa CJara, CA 95051.
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