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758 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28. NO. 7. JULY 1993 A CMOS Low-Distortion Fully Differential Power Amplifier with Double Nested Miller Compensation Sergio Pernici, Member, IEEE, Gerrnano Nicollini, and Rinaldo Castello, Senior Member, IEEE Abstract—A four-stage fully differential power amplifier using a double nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and THD is -S3 dB for a 6-VP –P differential output signal at 10 kHz and a load of 50 Q. With 8-0 load and for a 10-kHz, 4-VP–P output signal, THD is -68 dB. The chip area is 0.625 mm’ in a 1.5-~m single-poly, double-metal, n-well CMOS technology I. INTRODUCTION I N recent years many new very complex systems have been integrated into silicon chips. This has become possible especially through the use of new digital circuits with a continually increasing flexibility and precision. In this process many analog circuits have been substituted with digital ones. Although this tendency will continue, some analog blocks, especially those interfacing with the external world, cannot be replaced. One example is given by the power amplifiers or output buffers. Furthermore, as the precision and accuracy of DSP-based systems increase, the level of performance required from the analog interface circuits also increases. In ISDN voice terminal equipment and digital telephone sets, for instance, there is the necessity to drive loads of 50–100 0 and more than 100 nF for acoustic transducers, using CMOS technologies and a 5-V power supply [1]. Similar needs are present in battery-operated systems such as portable hi-fi systems and cellular and cordless phones, where sometimes power supply can be as low as 3 V. In all these cases general requirements are low distortion together with small die size and low quiescent current. However, it is difficult to satisfy all these requirements, especially regarding distortion, using previous design methodologies, In fact, for a buffer amplifier driving heavy loads, there is a trade-off between linearity on the one hand and power consumption and silicon area on the other. For instance, to improve open loop linearity while giving output currents of up to hundreds of milliamperes, very large widths (up to 10000 #m) are used for the output devices Manuscript received November 30, 1992; rewsed Febrnary 22, 1993. S. Pemici and G. Nicollini are with ST SGS-Thomson Microelectronics, 20041 Agrate Bnanza, Italy, R. Castello is with the Department of Electrical Engineering, Universdy of Pavia, 27100 Pawa, Italy.
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This note was uploaded on 09/19/2010 for the course EE 7326 taught by Professor Jimhellums during the Spring '08 term at University of Texas at Dallas, Richardson.

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