PMIC - 26 IEEE TRANSACTIONS ON SOLID-STATE CIRCUITS, VOL....

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Unformatted text preview: 26 IEEE TRANSACTIONS ON SOLID-STATE CIRCUITS, VOL. 35, NO. 1, JANUARY 2000 Active Capacitor Multiplier in Miller-Compensated Circuits Gabriel A. Rincon-Mora , Member, IEEE Abstract A technique is presented whereby the compen- sating capacitor of an internally compensated linear regulator, Miller-compensated two-stage amplifier, is effectively multiplied. Increasing the capacitance with a current-mode multiplier allows the circuit to occupy less silicon area and to more effectively drive capacitive loads. Reducing physical area requirements while producing the same or perhaps better performance is especially useful in complex systems where most, if not all, functions are integrated onto a single integrated circuit Die area in such systems is a luxury. The increasing demand for mobile battery-operated devices is a driving force toward higher integration. The enhanced Miller-compensation technique developed in this paper helps enable higher integration while being readily applicable to any process technology, be it CMOS, bipolar, or biCMOS. Further- more, the technique applies, in general, to amplifier circuits in feedback configuration. Experimentally, the integrated linear regulator (fabricated in a 1- m biCMOS process technology) proved to be stable for a wide variety of loading conditions: load currents of up to 200 mA, equivalent series resistance of up to 3 , and load capacitors ranging from 1.5 nF to 20 F. The total quiescent current flowing through the regulator was less than 30 A during zero load-current conditions. Index Terms Compensation amplifier, frequency capacitor multiplier, Miller compensation, regulator. I. INTRODUCTION A POPULAR technique for compensating amplifier feed- back circuits is the use of the Miller capacitor. The poles of a two-stage amplifier are split, one toward low frequencies and the other toward high frequencies, when this configuration is adopted. The pole at the output of the first stage becomes dominant. Fig. 1 illustrates a typical two-stage amplifier circuit model. Transconductors and are assumed to be ideal (infi- nite input and output impedance), resistors and model the effective impedance to ground at their corresponding nodes, and and are the load capacitor and the compensating capac- itor, respectively. The dominant low-frequency pole is located at node n1 ( ) and is defined by (1) where refers to the gain of the second stage. The nondomi- nant pole is located at the output. At high frequencies, capacitor shunts the output to node n1, thereby making the output tran- sistor look like a diode-connected device, in other words, look Manuscript received February 18, 1999; revised June 16, 1999. The author is with Power Management Products, Texas Instruments Incorpo- rated, Dallas, TX 75243 USA (e-mail: rincon-mora@ti.com)....
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PMIC - 26 IEEE TRANSACTIONS ON SOLID-STATE CIRCUITS, VOL....

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