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cap-free-ldo - IEEE JOURNAL OF SOLID-STATE CIRCUITS VOL 38...

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 10, OCTOBER 2003 1691 A Capacitor-Free CMOS Low-Dropout Regulator With Damping-Factor-Control Frequency Compensation Ka Nang Leung , Member, IEEE, and Philip K. T. Mok , Senior Member, IEEE Abstract— A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor- control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The pro- posed LDO has been implemented in a commercial 0.6- m CMOS technology, and the active chip area is 568 m 541 m. The total error of the output voltage due to line and load variations is less than 0.25%, and the temperature coefficient is 38 ppm/ C. Moreover, the output voltage can recover within 2 s for full load- current changes. The power-supply rejection ratio at 1 MHz is 30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 V/ , respectively. Index Terms— Damping-factor-control frequency compensa- tion, loop-gain stability, capacitor-free low-dropout regulator (LDO), CMOS voltage reference. I. I NTRODUCTION P OWER MANAGEMENT is necessary to reduce the standby power of portable applications such as cellular phones and PDAs. The low-dropout linear regulator (LDO) [1]–[4] is one of the most popular power converters widely used in power management. It is especially suitable for appli- cations that require low-noise and precision supply voltages with few off-chip components. With the rapid development of system-on-chip designs, there is a growing trend toward power-management integration. On-chip and local LDOs are utilized to power up subblocks of a system individually [5], and this can significantly reduce crosstalk, improve the voltage regulation, and eliminate load-transient voltage spikes from the bondwire inductances. In addition, system-on-chip designs with on-chip and local LDOs can reduce both board space and external pins significantly. Due to the emerging need of high-performance low-voltage LDOs for low-voltage mixed-signal systems, many researchers have recently proposed many advanced methods to improve the performance of LDOs. Rincon-Mora et al. proposed current-ef- ficient voltage buffer [1], forward-biased power transistor [1], Manuscript received January 6, 2003; revised June 9, 2003. The work was supported by the RGC Competitive Earmarked Research Grant, Hong Kong SAR Government, HKUST6022/01E. K. N. Leung and P. K. T. Mok are with the Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/JSSC.2003.817256 pole-zero doublet for load-regulation enhancement [2], and ca- pacitance multiplication [3]. Heisley et al. proposed using a DMOS power transistor [4]. Chevalerias et al. proposed using an nMOS power transistor with charge-pumped gate drive [6].
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