CICC-LDO - A Transient-Enhanced 20μA-Quiescent Transient...

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Unformatted text preview: A Transient-Enhanced 20μA-Quiescent Transient 20 Quiescent 200mA200mA-Load Low-Dropout Regulator LowWith Buffer Impedance Attenuation With Buffer Impedance Attenuation Mohammad Al-Shyoukh1,2 Al Hoi Lee2 Raul Perez Perez 1Texas 2University Instruments Inc. Dallas, TX, USA of Texas at Dallas, Dallas, TX, USA of Texas at Dallas Dallas TX USA Outline Motivations Motivations Proposed Proposed Buffer Impedance Attenuation Circuit Circuit Implementations Silicon Results Silicon Results 2 Motivations Motivations Power Power Management ICs (PMICs) are important in huge and growing market for portable electronics (e.g. MP3 players, cell phones) (e.g. MP3 players, cell phones) LDOs LDOs are a major building block in PMICs to provide clean voltages to other noise clean voltages to other noise-sensitive systems systems LDO requirements in PMICs: LDO requirements in PMICs: 200mA full200mA full-load current Low Low quiescent current: Iq < 20μA Ceramic output capacitor as small as 1 μF for low-cost ow-cos advantage advantage Maximum Maximum transient output variation within 2% of output voltage for the maximum load output voltage for the maximum load-step change change 3 General LDO Structure P1 P2 P3 Buffer Buffer stage is needed to drive power FET Three Three poles P1, P2, and P3 in LDO structure 4 Buffer Buffer Stage Requirements For For low quiescent current Level shifting toward supply to enable complete Level shifting toward supply to enable complete turn turn off of power FET under no-load condition no- For For stability Small Small rob for pushing P2 to high frequency Small Cib for pushing P1 to high frequency hi Question: How to achieve low quiescent Question: How to achieve low quiescent current current and stability simultaneously? 5 Conventional Source-Follower SourceBuffer Implementation Buffer Implementation Stability Issues: Moving Moving P2 to higher frequency by increasing gm21 Increases Increases LDO quiescent current or Increases Increases Cib & P1 moves to moves to lower lower frequency I21 Mp P2 P1 Cib M21 rob If using ESR zero Degrades Degrades transient undershot/overshoot performances 6 Buffer Buffer Impedance Attenuation (1) Add local feedback to the source follower Q20 creates shunt Q20 creates shunt feedback feedback hi higher P2 as effective rob is decreased higher higher P1 as smaller (W⋅L)M21 and smaller Cib Q20 Q20 can be replaced by nMOS I22 I21 Mp P2 P1 M21 Q20 M23 M22 7 Buffer Impedance Attenuation (2) The The effective output resistance of the buffer: where gm21 : the transconductance of source follower M21 βQ21 : current gain of added npn device P2 = 1/(rob⋅Cg) moves to higher frequency by the current gain of the npn device where Cg is total capacitance at the buffer output 8 1 rob = g m21 ⋅ (1 + βQ20 ) Buffer Buffer Impedance Attenuation (3) M24 M24 further reduces rob 1 1 rob = // g m21 ⋅ (1 + βQ20 ) g m24 Both Both M24 & M25 allow that rob decreases as load current increases ⇒ P2 increases with the load current 9 Frequency Compensation of Proposed LDO P1 P3 The The proposed LDO is a two gain-stage structure gainCurrent-buffer compensation scheme for splitting P1 and an P3 through Cc and M3 10 Loop Loop Gain (LG) of Proposed LDO LG = β g m1g mp ro1Ro s 2C1CL ro1Ro + sRo (CL + Cc ro1g mp ) + 1 11 Phase Margin (PM) ⎛g r C ⎞ PM = 90 0 − tan −1 ⎜ m1 o1 ⋅ 1 ⎟ ⎜4 Cc ⎟ ⎝ ⎠ PM PM of LDO increases as C1 decreases The proposed buffer decreases the required The proposed buffer decreases the required C1 by reducing by reducing (W (W⋅L) of source-follower transistor and thus improves stability source12 Bode Bode Plots of Proposed LDO First order rolloff behavior under different load First order rolloff behavior under different load-current cases cases Stability Stability of the proposed LDO is achieved 13 Full LDO Schematic LDO Schematic Proposed Buffer 14 Micrograph of LDO Micro LDO LDO implemented in 7V, twin-well 0.35μm twinCMOS process Vertical Vertical parasitic npn β = 20 ~ 40 20 40 LDO LDO area = 0.264 mm2 Integrated on custom Integrated on custom PMIC PMIC for a portable application 15 Proposed LDO Silicon Results: Vout = 1.8V, CL = 1μF 200mA 1mA Load Current < 15mV overshoot/undershoot for IL changing from 1mA to 200mA (pulse rise & fall time of 100ns) 200 ti 100 < 24 mV dc variation mainly due to single bondwire 16 0.55mm 0.48mm CL = 1μF < 15 mV Output Voltage < 24 mV Total ΔVout < 39mV Silicon Silicon Results: Vout = 1.8V, CL = 1μF Total ΔVout = 54mV out Under Under 20mV undershoot for IL changing from 0 to 200mA 34mV 34mV dc variation mainly due to single bondwire 17 Silicon Results: Vout = 3.3V, Line Step 1V Line Step = 1V < 3mV of ΔVout due to line step of 1V at IL = 1mA 3mV of to line step of 1V at 1mA < 15mV of ΔVout at IL = 200mA 15mV at 18 Performance Performance Summary Full Load Current Load Current Iq (no load) Iq (full load) PSRR up to 20 kHz Transient Response Response 0 – 200mA Step Tran. Response 1 – 200mA Step St DC Load Regulation 0 – 200mA Dropout Voltage (Vdo) Die Area Area Technology 200mA 20μA 350μA > 50dB (simulation) Undershoot < 1% 1% CL = 1μF Undershoot < 0.5% CL = 1μF 33 mV Vout = 1.8V (single bondwire) 0.2 V 0.264 mm2 mm 0.35μm CMOS 19 Performance Comparisons with Previously Reported LDOs Previously Reported LDOs JSSC 1998 [1] Technology (μm) Vdo (Vin-Vout) (V) Iomax (mA) Iq (mA) Current Efficiency Efficiency (%) ΔVout (mV) TR (μs) (CL⋅ ΔVout)/Iomax CL (μF) ESR Zero Required Zero Required FOM (ns) TR⋅(Iq/Iomax) JSSC 2000 [2] 1.0 N. A. 200 0.030 N.A. 220 1.1 1 Yes 0.165 JSSC 2003 [3] 0.6 0.2 100 0.038 99.96 130 2 10 Yes 4.9 JSSC 2005 [4] 0.09 0.3 100 6 94.3 90 0.00054 0.00060 No 0.032 This work 0.35 0.2 200 0.020 99.8 54 0.27 1 No 0.027 2.0 0.3 50 0.023 99.5 19 1.8 4.7 No 8.2 20 References References 1. 2. 3. G. A. Rincon-Mora and P. E. Allen, “A low-voltage, low quiescent Rinconlowcurrent low drop-out regulator,” IEEE J. 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