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Unformatted text preview: 1100 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006 Design of Charge Pump Circuit With Consideration of Gate-Oxide Reliability in Low-Voltage CMOS Processes Ming-Dou Ker , Senior Member, IEEE , Shih-Lun Chen , Student Member, IEEE , and Chia-Shen Tsai Abstract A new charge pump circuit with consideration of gate- oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping ef- ficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal oper- ating power supply voltage (VDD). Two test chips have been imple- mented in a 0.35- m 3.3-V CMOS process to verify the new pro- posed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply @ VDD a Q Q V A , which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping effi- ciency and no overstress across the gate oxide of devices. Index Terms Body effect, charge pump circuit, gate-oxide reli- ability, high-voltage generator, low voltage. I. INTRODUCTION C HARGE pump circuits have been often used to generate dc voltages those are higher than the normal power supply voltage (VDD) or lower than the ground voltage (GND) of the chip. Charge pump circuits are usually applied to the nonvolatile memories, such as EEPROM or flash memories, to write or to erase the floating-gate devices . In addition, charge pump circuits had been used in some low-voltage designs to improve the circuit performance , . The four-stage diode charge pump circuit using the pn-junction diodes as the charge transfer devices is shown in Fig. 1(a). The charges are pushed from the power supply (VDD) to the output node ( ), stage by stage. Thus, the output voltage of the charge pump circuit can be pumped high. The voltage fluctuation of each pumping node can be expressed as (1) where is the voltage amplitude of the clock signals, is the pumping capacitance, is the parasitic capacitance at each pumping node, is output current, and is the clock frequency. If and are small enough and is large Manuscript received June 17, 2005; revised November 4, 2005. The authors are with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, 1001 Ta-Hsueh Road, Hsinchu, Taiwan 30050, R.O.C. (e-mail: firstname.lastname@example.org)....
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