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Unformatted text preview: 1136 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005 Switching Noise and Shoot-Through Current Reduction Techniques for Switched-Capacitor Voltage Doubler Hoi Lee , Member, IEEE, and Philip K. T. Mok , Senior Member, IEEE Abstract— Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doublers based on cross-coupled structure are presented. The intuitive analysis of the shoot-through current and switching noise generation processes in the doubler is first reported. Break-before-make mechanism is adopted to minimize the shoot-through current, thereby greatly reducing the no-load supply current dissipation and improving the light-load power efficiency of the voltage doubler. In addition, by employing gate-slope reduction technique at the serial power transistor during turn-on, the switching noise of the voltage doubler is significantly lowered. Two voltage doublers with and without the proposed circuit tech- niques have been fabricated in a 0.6- m CMOS process. Experi- mental results verify that the total supply current at no-load con- dition of the proposed voltage doubler is reduced by twofold and its switching noise is decreased by 2.5 times. Index Terms— Break-before-make mechanism, charge pump, dc–dc converter, shoot-through current, switched-capacitor power converter, switching noise, voltage doubler. I. INTRODUCTION I N RECENT years, switched-capacitor voltage doublers capable of delivering tens of milliampere load current are growing in great demand, as they are mandatory in the power management ICs for battery-powered portable applications. For example, these doublers are widely utilized for providing a higher supply voltage to the general-purpose I/O circuitries in the mobile phone. Among different types of switched-capacitor voltage doublers, the cross-coupled voltage doubler is the most commonly used topology and its circuit implementation is shown in Fig. 1(a) –. The cross-coupled voltage doubler operates at twice the switching frequency such that either the ripple voltage or the size of the load capacitor can be halved. The voltage doubler, which is driven by the two-phase nonoverlapping clock signals as shown in Fig. 1(b), contains a voltage booster circuit with a pair of cross-coupled nMOS Manuscript received July 29, 2004; revised December 21, 2004. This work was supported by the Research Grant Council of Hong Kong, SAR Government, China, under Project HKUST6150/03E. H. Lee was with the Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong. He is now with Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX 75083-0688 USA (e-mail: email@example.com)....
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This note was uploaded on 09/19/2010 for the course EE 6378 taught by Professor Hle during the Spring '10 term at University of Texas at Dallas, Richardson.
- Spring '10