This preview shows pages 1–2. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: 410 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 3, MARCH 1998 A High-Efficiency CMOS Voltage Doubler Pierre Favrat, Associate Member, IEEE, Philippe Deval, and Michel J. Declercq, Senior Member, IEEE Abstract— A charge pump cell is used to make a voltage doubler using improved serial switches. A complete power efficiency theory is presented which fits the measurements. The importance of capacitors is shown with plots of power efficiency versus load and stray capacitors. Several problems arising at low voltage or high frequency are developed and some optimizations are presented. The substrate current is totally suppressed by the technique of bulk commutation. A power efficiency of 95% has been reached using external capacitors. A fully integrated charge pump is also presented and shows a maximum power efficiency of 75%. Index Terms— Charge pump, dc–dc converter, power effi- ciency, voltage doubler. I. INTRODUCTION I N the framework of deep submicrometer technologies and low power applications where the supply voltage is often reduced to 1 or 2 V, the voltage doubler appears as a very important block. It can be used in low-voltage mixed-mode circuits to supply the analog part or the most critical analog blocks. This paper is focused on the power efficiency of a new CMOS voltage doubler. A circuit, viable in a CMOS technology as a clock booster, has been proposed in . This circuit has the particularity of cross-connecting NMOS transistors from their source (Fig. 1). This use of NMOS is efficient, not only because of higher carrier speed, but particularly since it provides automatic reverse bias of the junctions. Unfortunately, with this circuit, to obtain a doubled dc output we need a serial switch, and this can only be achieved by a PMOS transistor to avoid the drop. The problem arising from the use of PMOS is to ensure the reverse bias of the junctions. A solution was proposed in  using two charge pump blocks, one for the supply and the other to boost the bulk voltage of P1 (Fig. 2). This solution prevents a direct biasing of the P1 junctions but does not solve the problem for P2. In the second charge pump, the P2 bulk is connected only to a capacitor, and is thus floating. Therefore, P2’s bulk voltage will rise with junction current. This implies that the drain-to- bulk voltage of P2 stays close to the junction potential. The result is a quasi-permanent charge loss. Of course, this loss is not very important compared to the whole efficiency of the Manuscript received August 5, 1997; revised October 17, 1997. This work was supported by the Swiss Program for Scientific Research Encouragement CERS. Part of this work was presented at the CICC’97 and ISCAS’97 Conferences....
View Full Document
This note was uploaded on 09/19/2010 for the course EE 6378 taught by Professor Hle during the Spring '10 term at University of Texas at Dallas, Richardson.
- Spring '10