diff_lna2 - Proceedings of the Asia-Pacific Microwave...

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Proceedings of the Asia-Pacific Microwave Conference 2006 Copyright 2006 IEICE A CMOS Ultra-Wideband Differential Low Noise Amplifier Timothy B. Merkin, Sungyong Jung, Jean Gao, * Youngjoong Joo The University of Texas at Arlington, Arlington TX, USA 76019; * Arizona State University, Tempe, AZ, USA 85287 Tel: +1-817-272-1210, E-mail: [email protected] Abstract — This paper presents the design and simulation of a CMOS Ultra-wideband Low noise Amplifier. In the design, specific architecture decisions were made in consideration of system-on-chip implementation. The basic architecture of the LNA designed herein exhibits a differential amplifier core with active input and output impedance matching. Simulations reveal that the LNA maintains a gain of 16.7 dB with a ±0.3 dB ripple over the band of 3.1-6.0GHz. Despite the use of an active input matching stage, the LNA achieved a simulated noise figure ranging from 3.0-3.5 dB over the band of operation. The input and output active matching stages maintain less than -10 dB reflection coefficients, thus successfully matching with 50 over the bands of 3 – 12GHz and 3 – 17GHz, respectively. Index Terms — Ultra-Wideband, low noise amplifiers, communications, analog integrated circuits. I. INTRODUCTION Despite its long history in radio and radar systems, Ultra-Wideband (UWB) technology just recently stands poised to offer unprecedented high data rates combined with low power consumption to many different commercial application areas. This recent push for the development of UWB systems has been fueled by the Federal Communications Commission’s (FCC) decision to allow unlicensed spectrum usage of 3.1 – 10.6GHz in 2002. The availability of this “huge bandwidth” encourages a plethora of bandwidth demanding, low power applications such as Wireless Personal Area Networks (WPANs), sensor networks, imaging systems, vehicular radar systems, and etc. Also of late, there has been a thrust in research to develop entire systems-on-chip (SoC). And because of its cost advantage and ease of integrating high-performance digital circuits and high-speed analog/RF circuits, CMOS technology has emerged as the top technology for SoCs. However, one of the biggest impediments to CMOS SoC development is the “noisy” influence (sometimes called substrate noise) of nearby digital circuitry on sensitive analog circuitry. Although there have been several other methods proposed for minimizing the effect of substrate noise, a differential architecture is known to aid in rejection of some of this type of noise. By rejecting this noise, differential architectures increase the robustness of the analog circuitry. The architecture of the Low Noise Amplifier (LNA) developed in this paper was motivated by these issues. Considerable research has developed CMOS Low Noise Amplifiers (LNA) with exceptional performance characteristics suitable for the analog front-end of a UWB wireless system [1]-[8]. One of these LNAs employs a differential architecture [7], but the power consumption and noise figure are relatively high and can be improved upon.
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This note was uploaded on 09/19/2010 for the course EE 7V88 taught by Professor Dr.karba during the Fall '09 term at University of Texas at Dallas, Richardson.

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diff_lna2 - Proceedings of the Asia-Pacific Microwave...

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