diff_lna3_tsmc - 18.2 GHz Differential Low Noise Amplifier...

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18.2 GHz Differential Low Noise Amplifier for On- chip Ultra Wide Band Transceiver Md. Ariful Haque, Mir Saddam Hossain, Shamsuddin Ahmed and A.B.M. H. Rashid, Senior Member IEEE Department of Electrical & Electronic Engineering, Bangladesh University of Engineering & Technology, Dhaka-1000, Bangladesh. E-mail: arif6008gyahoo.com. Abstract- In this paper an 18.2 GHz differential low noise amplifier (LNA) is proposed for use in on chip ultra wide band transceiver. We used TSMC 0.35 gm process MOSFET model parameters and the simulations are carried out using Cadence Spectre simulator. The single stage differential LNA shows 22.06 dB voltage gain at 18.2 GHz with a operating frequency band of 7.87 GHz. It achieves 0.4162 dB noise figure, Sll = -16.701 dB, S12 = -6.46916 dB, S21 = 3.61662 dB, S22 = -7.7075 dB. Its 1 dB compression point is -14.599 dBm and input referred IP3 is -10.9778 dBm. The circuit operates at +1 V and -1 V supply voltage and consumes 0.50 mW power. I. INTRODUCTION In to-days advanced CMOS process, not the device delay but the delay due to the interconnected parasitic hurts the circuits and system performance [ 1-2]. The speed limitations of conventional interconnect metal lines have led to the concept of on- chip wireless interconnections using integrated antenna on Si [3-5]. For high data transmission rates and multiple access capabilities of the wireless interconnect system, wideband characteristics of an integrated transmitter and receiver are required. To achieve these characteristics a time hopping ultra wide band (UWB) system has been proposed recently [6]. As the first block in a UWB receiver, it is required that the Low Noise Amplifier (LNA) should have sufficient gain, low noise figure, high linearity and good input output matching. A high gain and low noise figure is required to suppress noise from the received signal as much as possible providing high gain to the succeeding stage such as a mixer. A high linearity is required when the transmitter and receiver are close enough in order to accommodate the strong signal. As this LNA is designed to be used in on chip UWB transceiver it should also consume low power. Since on-chip integrated antenna will feed the LNA directly it should have high operating frequency in order to reduce the antenna size. If the size of the dipole antenna is limited to 2 mm in length, the operating frequency of the LNA should be 18 GHz [4]. Again the gain characteristics of the antenna [4} and its use in a UWB system [6] require that the LNA should have ultra wide bandwidth. CMOS LNA for use in GPS application and operating at 1.3 GHz and 1.5 GHz input frequencies have been reported in [7] and [8], respectively. CMOS LNA operating at 5 GHz range has been reported in [9]-[10]. A LNA operating at 26-42 GHz has been reported in [11] but it is built on SOI-CMOS process. UWB LNAs have been reported at 3-5 GHz bandwidth [12] and 3.1-10.6 GHz bandwidth [13].
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