diff_lna4 - Proceedings of Asia-Pacific Microwave...

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Proceedings of Asia-Pacific Microwave Conference 2006 A 5.8 GHz 1.7 dB NF Fully Integrated Differential Low Noise Amplifier in CMOS Lars Aspemyr 1,2 , Henrik Sjöland 2 , Harald Jacobsson 1 , Mingquan Bao 1 , Geert Carchon 3 1 Ericsson AB, Mölndal, Sweden. 2 Lund University, Sweden. 3 IMEC, Leuven, Belgium Tel: +46-31-747-3442, E-mail: [email protected] Abstract This work presents a fully integrated differential 5.8 GHz low-noise amplifier (LNA). The LNA is fabricated in a 90 nm RF-CMOS process and has a power gain of 12.5 dB, an IIP3 of 4dBm, and a noise figure of 1.7 dB consuming 14 mA from a 1.2 V supply. Compared to previously reported differential CMOS designs this LNA show lower noise figure and better linearity. Index Terms Low noise amplifier, LNA, differential, CMOS, cascode. I. INTRODUCTION There is a great interest in wireless systems with carrier frequency in the 1-10 GHz region. 802.11a, b, g (WLAN) and Bluetooth transceivers are used today in consumer products in mass production and WiMAX, UWB and ZigBee are upcoming wireless standards in this frequency band. Thanks to the downscaling of transistor dimensions the high frequency performance of CMOS is today sufficient for use in design of front-ends for these radio systems, which is apparent when publications and products are studied. An advantage of the CMOS technology is that DSPs, ADCs and DACs can be integrated on the same chip as the RF parts. To build a noise tolerant system on a chip a differential realization of the LNA can be an attractive alternative. If the carrier must be rejected, the receiver often consists of double balanced mixers, requiring a differential input signal. This receiver topology is shown in Fig. 1. Fig. 1. Block diagram of a receiver. To convert the single ended signal from the antenna to the wanted differential signal a balun is required. An on-chip balun will consume expensive chip area and will also introduce losses in the signal path. A low loss off-chip balun is therefore often preferred; this will however require a differential on-chip LNA. Differential LNAs presented in publications [1]-[4] often show much worse noise performance than single ended LNAs [5]-[9]. No fundamental reason to this exists, if the higher power consumption of the differential topology is accepted similar noise performance can be reached. To further analyze this topic and to demonstrate the abilities of 90 nm CMOS, a fully integrated differential LNA at 5.8 GHz is designed and fabricated in this work. II. CIRCUIT DESIGN The circuit is a differential design using cascoded n-channel MOS transistors, shown in Fig. 2. An advantage with the differential realization is a better rejection of common mode signals and a design that is less sensitive to the impedance of the ground path.
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This note was uploaded on 09/19/2010 for the course EE 7V88 taught by Professor Dr.karba during the Fall '09 term at University of Texas at Dallas, Richardson.

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diff_lna4 - Proceedings of Asia-Pacific Microwave...

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