Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
A LINEARIZATION TECHNIQUE FOR RF LOW NOISE AMPLIFIER Chunyu Xin, Edgar S´anchez-Sinencio Department of Electrical Engineering College Station, TX 77843 ABSTRACT A LNA linearization technique derived from multi-gated conFgu- ration using bipolar transistors in CMOS technology is proposed. Bipolar transistor is used to replace the auxiliary MOS transis- tor to achieve higher operational speed. Both single-ended and differential applications are investigated. Simulation shows that this method is competitive with already reported low noise ampli- Fers . ±or 3GHz of frequency operation, the single-ended struc- ture achieves +15dBm IIP3 with 8.9mW power consumption, and the differential architecture can achieve +14dBm IIP3 with 21mW power consumption. 1. INTRODUCTION Linearity is a key issue in R± systems. A circuit’s non-linearity brings a lot of problems such as inter-modulation and gain com- pression. Micro-processor technique development makes the CMOS process much cheaper than others. The system-on-chip target, also demands CMOS technology. ±or the same current consumption, NMOS transistors are more linear than bipolar transistors. Still the linearity of MOS transistors can not meet the stringent require- ments of state-of-the-art applications such as CDMA/AMPS. Linearity based on negative feedback is not suitable for high frequency applications due to stability issues and gain reduction. Thus, a lot of linearization techniques that focus on linearizing MOS±ET transistors are introduced. The basic idea of lineariza- tion here is to use additional transistor’s non-linearity to compen- sate or cancel the nonlinearity of the main operation device using a feed-forward technique. The conventional way involves MOS transistors working in triode or weak inversion to provide lineariza- tion. With the development of technology, bipolar is available in CMOS technology. Although its performance is not as good as that in BiCMOS process, it is sufFcient to use to provide linearization. The proposed linearization technique is derived from multi-gated linearization. ±irst in Section 2 the multi-gated approach is briefly reviewed and its problem is identiFed. Then Section 3 presents the linearization method for single-ended and differential applica- tions. Section 4 gives the simulation results to prove that the idea is feasible. ±inally conclusions are drawn in Section 5. 2. REVIEW OF MULTI-GATED LINEARIZATION TECHNIQUE Low noise ampliFers (LNA) have stringent requirements on oper- ation frequency, noise, and linearity. Therefore, the LNA usually uses a minimum number of transistors. ±or example, a single- ended LNA usually contains one or two transistors in its main signal path. In order to improve LNA’s linearity, more compo- nents have to be introduced into the signal path. Degeneration and shunt-series feedback are traditionally used. A method based on multi-gated transistor third-order cancellation is discussed in[1]- [3]. The basic idea is to interconnect two optimally biased MOS
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 4


This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online