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Unformatted text preview: Introduction to Embedded Microcomputer Systems Lecture 8.1 Jonathan W. Valvano Computers in the future may weigh no more than 1.5 tons Popular Science, 1949 Recap Debugging: Monitor, dump TExaS Real 9S12DP512 Overview Addition and subtraction set CCR bits Subtraction used for conditional branching Condition code register (CC or CCR) C set after an unsigned add if the answer is wrong V set a signed add if the answer is wrong bit name meaning after add or sub N negative result is negative Z zero result is zero V overflow signed overflow C carry unsigned overflow Table 3.16. Condition code bits. 96+64 224+64 64 128 192 255 96 160 +64 32 224 +64 64 128 192 255 Figure 3.20. Unsigned number wheel. 16064 3264 6464 64 128 192 255 96 160 32 224 64 128 192 255 Figure 3.22. Unsigned number wheel. Observation: The carry bit, C, is set after an unsigned addition or subtraction when the result is incorrect. 32+64 96+64 1 +64 64 12764128 3232 96961 64 12764128 +64 Figure 3.23. Signed number wheel. Introduction to Embedded Microcomputer Systems Lecture 8.2 Jonathan W. Valvano 3264 9664 64641 64 12764128 3232 96961 64 12764128 Figure 3.24. Signed number wheel Observation: The overflow bit, V, is set after a signed addition or subtraction when the result is incorrect. Let the result R be the result of the addition A+B. N bit is set if unsigned result is above 127 or if signed result is negative. N = R7 Z bit is set if result is zero. Z = R0 &amp; R1 &amp; R2 &amp; R3 &amp; R4 &amp; R5 &amp; R6 &amp; R7 V bit is set after a signed addition if result is incorrect V = R7 &amp; B7 &amp; A7 R7 &amp; B7 &amp; A7 + C bit is set after an unsigned addition if result is incorrect C = R7 &amp; B7 R7 &amp; A7 B7 &amp; A7 + + Let the result R be the result of the subtraction AB....
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This note was uploaded on 09/19/2010 for the course E E 16280 taught by Professor Valvano during the Fall '10 term at University of Texas at Austin.
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