aLec26_SCIinterrupt - Introduction to Embedded...

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Introduction to Embedded Microcomputer Systems Lecture 26.1 Jonathan W. Valvano Recap Serial communication; what does the frame look like SCI shift register versus SCI data register How RDRF is set; how RDRF is cleared How TDRE is set; how TDRE is cleared Overview Baud rate vs bandwidth Latency vs real time Synchronization between computers SCI interrupts Classification Simplex: data flows in one direction Half-duplex: data flows in both ways, one way at a time Full-duplex: data can flow both ways at the same time Lab 7 hardware allows for full duplex communication it is used in a simplex manner PS3 PS2 Ground 11 14 13 12 MAX232A PS3 PS2 Ground 9S12DP512 SCI1 TxD RxD SG 11 14 13 12 MAX232A 9S12DP512 SCI1 TxD RxD SG Shift Shift Data Data Shift Shift Data Data Lab 7 Configuration Things to remember There are two data registers at the same address SCI1DRL The transmit SCI1DRL is write only The receive SCI1DRL is read only There are two shift registers The transmit shift register is connected to PS3 output The receive shift register is connected to PS2 input Frames have 1 start, 8 data and 1 stop bit 5V 0V b 0 b 1 b 2 b 3 b 4 b 5 b 6 serial port b 7 one frame start stop Figure 8.1. A 10-bit serial data frame(with M=0). Review of how SCI works To transmit, the software (busy-wait synchronization) Waits until TDRE is 1 (meaning data register is empty) Writes data to SCI1DRL To transmit, the hardware Moves 8-bit data from data register to shift register Adds start bit at front (0) Puts stop bit (1) at end Shifts the 10-bit frame out PS3 at the baud rate To receive, the software (busy-wait synchronization) Waits until RDRF is 1 (meaning data register has data)
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Introduction to Embedded Microcomputer Systems Lecture 26.2 Jonathan W. Valvano Reads data from SCI1DRL To receive, the hardware Waits for a 1 to 0 edge defining the start bit
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aLec26_SCIinterrupt - Introduction to Embedded...

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