ARMintro - Copyright 2002 ARM LTD. All rights reserved. Not...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
Copyright © 2002 ARM LTD. All rights reserved. Not to be reproduced by any means without prior written consent. T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D RISC Architecture Introduction Case study: ARM7TDMI Processor Core 2 RISC Architecture Introduction Embedded microprocessors Microprocessor
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Copyright © 2002 ARM LTD. All rights reserved. Not to be reproduced by any means without prior written consent. 3 RISC Architecture Introduction ARM7TDMI Core Signals ARM7TDMI Core MCLK nIRQ nFIQ nRESET BUSEN BIGEND ISYNC nWAIT VDD VSS APE DBE Coprocessor Interface Memory Management Memory Interface ABORT nOPC CPB CPA nCPI nTRANS nM[4:0] MAS[1:0] nRW nMREQ LOCK SEQ nENOUT A[31:0] DOUT[31:0] DIN[31:0] D[31:0] Power Bus Control Clocks Configuration Interrupts 4 RISC Architecture Introduction ARM7TDMI Block Diagram ARM7TDM Core TAP Controller JTAG Interface Data Bus Control Signals D[31:0] Address Bus A[31:0] DIN[31:0] DOUT[31:0] Bus Splitter Embedded ICE Logic
Background image of page 2
Copyright © 2002 ARM LTD. All rights reserved. Not to be reproduced by any means without prior written consent. 5 RISC Architecture Introduction Data processing Instructions ± Consist of : ± Arithmetic: ADD ADC SUB SBC RSB RSC ± Logical: AND ORR EOR BIC ± Comparisons: CMP CMN TST TEQ ± Data movement: MOV MVN ± These instructions only work on registers, NOT memory. ± Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2 ± Comparisons set flags only - they do not specify Rd ± Data movement does not specify Rn ± Second operand is sent to the ALU via barrel shifter. 6 RISC Architecture Introduction Single register data transfer LDR STR Word LDRB STRB Byte LDRH STRH Halfword LDRSB Signed byte load LDRSH Signed halfword load ± Memory system must support all access sizes ± Syntax: ± LDR {<cond>}{<size>} Rd, <address> ± STR {<cond>}{<size>} Rd, <address> e.g. LDREQB
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Copyright © 2002 ARM LTD. All rights reserved. Not to be reproduced by any means without prior written consent. 7 RISC Architecture Introduction ± Branch : B{<cond>} label ± Branch with Link : BL{<cond>} subroutine_label ± The processor core shifts the offset field left by 2 positions, sign-extends it and adds it to the PC ± ± 32 Mbyte range ± How to perform longer branches? 28 31 24 0 Cond 1 0 1 L Offset Condition field Link bit 0 = Branch 1 = Branch with link 23 25 27 Branch instructions 8 RISC Architecture Introduction Multiplier The ARM7TDM Core Instruction Decoder Address Incrementer nRESET nMREQ SEQ ABORT nIRQ nFIQ
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 09/21/2010 for the course ECE 4180 taught by Professor Staff during the Spring '08 term at Georgia Institute of Technology.

Page1 / 12

ARMintro - Copyright 2002 ARM LTD. All rights reserved. Not...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online