ARMwksp - 1 The ARM Architecture 2 Joe Bungo Graduated from...

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Unformatted text preview: 1 The ARM Architecture 2 Joe Bungo Graduated from the University of Texas Austin in May 2003 Bachelors of Science in Computer Science 3 years in the Software Applications Engineering group and in the University Relations group of ARM Email: Joe.Bungo@arm.com 3 Agenda Introduction to ARM Ltd ARM Architecture/Programmers Model Data Path and Pipelines AMBA Development Tools 4 ARM Ltd Founded in November 1990 Spun out of Acorn Computers Designs the ARM range of RISC processor cores Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers. ARM does not fabricate silicon itself Also develop technologies to assist with the design- in of the ARM architecture Software tools, boards, debug hardware, application software, bus architectures, peripherals etc 5 ARM Partnership Model 6 ARM Powered Products 7 Agenda Introduction to ARM Ltd ARM Architecture/Programmers Model Data Path and Pipelines AMBA Development Tools 8 Architecture Revisions 1998 2000 2002 2004 time version ARMv5 ARMv6 1994 1996 2006 V4 StrongARM ARM926EJ-S XScale TM ARM102xE ARM1026EJ-S ARM9x6E ARM92xT ARM1136JF-S ARM7TDMI-S ARM720T XScale is a trademark of Intel Corporation ARMv7 (Future) SC100 SC200 ARM1176JZF-S ARM1156T2F-S 9 Data Sizes and Instruction Sets The ARM is a 32-bit architecture. When used in relation to the ARM: Byte means 8 bits Halfword means 16 bits (two bytes) Word means 32 bits (four bytes) Most ARMs implement two instruction sets 32-bit ARM Instruction Set 16-bit Thumb Instruction Set Jazelle cores can also execute Java bytecode 10 10 10 Processor Modes The ARM has seven basic operating modes: User : unprivileged mode under which most tasks run FIQ : entered when a high priority (fast) interrupt is raised IRQ : entered when a low priority (normal) interrupt is raised Supervisor : entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations Undef : used to handle undefined instructions System : privileged mode using the same registers as user mode 11 11 11 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr FIQ IRQ SVC Undef Abort User Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp)...
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This note was uploaded on 09/21/2010 for the course ECE 4180 taught by Professor Staff during the Spring '08 term at Georgia Institute of Technology.

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ARMwksp - 1 The ARM Architecture 2 Joe Bungo Graduated from...

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