Prelim_exam_sol_f06

# Prelim_exam_sol_f06 - ECE PHD PRELIMINARY EXAMINATION...

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Unformatted text preview: ECE PHD PRELIMINARY EXAMINATION SOLUTIONS – FALL 2006 EXAM 2 Problem 1 (Core: CompE-ECE2030) Prelim Problem based on ECE2030/2031 material Design a synchronous finite state machine that produces the follow (binary-encoded) output sequence when an external control signal (X) is set to zero: Z = 0 (also Reset), 1, 5, 6, 3, 2, 4, (returning to 0 on the next count). Here "Z" represents the decimal equivalent three-bit output code word (Z2,Z1,Z0). For example, Z=6 is represented by (Z2,Z1,Z0)=(1,1,0). The same circuit should count in the following (different) sequence when X=1: 0 (Reset), 4, 2, 3, 6, 5, 1, (returning to 0 on the next count) For this problem, use positive edge-triggered D-type flip flops for the state register and use the state of the register to define the output code. (a) Construct a state transition table. (b) Construct Karnaugh maps for the flip flop input functions. (c) Express the flip-flop input functions in minimum-sum of products (SOP) form. SOLUTION: (a) Based on the problem statement, we can construct the state transition table as follows: _______PS________ _______NS________ __DECIMAL__ X Z2 Z1 Z0 Z2+ Z1+ Z0+ PS NS(+) 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 1 1 5 0 0 1 1 0 1 0 3 2 0 0 1 0 1 0 0 2 4 0 1 0 0 0 0 0 4 0 0 1 0 1 1 1 0 5 6 0 1 1 1 X X X 7 X(don’t care) 0 1 1 0 0 1 1 6 3 1 1 0 0 0 1 0 4 2 1 1 0 1 0 0 0 5 1 1 1 1 1 X X X 7 X 1 1 1 0 1 0 1 6 5 1 0 0 0 1 0 0 0 4 1 0 0 1 0 0 0 1 0 1 0 1 1 1 1 0 3 6 1 0 1 0 0 1 1 2 3 3 SOLUTION (continued): (b and c) From this table, we can construct Karnaugh Maps (one for each of the 3 next-state functions): 1 00 01 11 10 X Z2 Z1 Z0 00 01 11 10 X X Z0+ = X’Z1’Z2’ + Z1Z2 + XZ0’Z1 X Z0 Z1 Z2 1 1 1 1 1 00 01 11 10 X Z2 Z1 Z0 00 01 11 10 X X Z0+ = X’Z1’Z2’ + Z1Z2 + XZ0’Z1 X Z0 Z1 Z2 1 1 1 1 1 00 01 11 10 X Z2 Z1 Z0 00 01 11 10 X X Z1+ = X’Z0Z2 + X’Z1Z2 + X Z1Z2’ + Z0Z1 + XZ0’Z1’Z2 X Z0 Z1 Z2 1 1 1 1 1 1 00 01 11 10 X Z2 Z1 Z0 00 01 11 10 X X Z1+ = X’Z0Z2 + X’Z1Z2 + X Z1Z2’ + Z0Z1 + XZ0’Z1’Z2 X Z0 Z1 Z2 1 1 1 1 1 1 00 01 11 10 X Z2 Z1 Z0 00 01 11 10 X X Z2+ = X’Z0Z1’ + X’Z0Z2 + XZ0Z1 + XZ1Z2 + X’Z0Z1Z2’ + XZ0Z1’Z2’ X Z0 Z1 Z2 1 1 1 1 1 1 00 01 11 10 X Z2 Z1 Z0 00 01 11 10 X X Z2+ = X’Z0Z1’ + X’Z0Z2 + XZ0Z1 + XZ1Z2 + X’Z0Z1Z2’ + XZ0Z1’Z2’ X Z0 Z1 Z2 1 1 1 1 1 4 Problem 2 (Core: CompE-ECE2030) 5 Problem 3 (Core: CompE-ECE3055) 6 Problem 4 (Core: CompE-ECE3060) Solution: d c b a F + + = ) ( 7 Problem 5 (Core: E&M-ECE3025) 8 Problem 6 (Core: E&M-ECE3065) 9 Problem 7 (Core: EDA-ECE2040) 10 11 Problem 8 (Core: EDA-ECE3050) 12 13 Problem 9 (Core: Power-ECE3070) Fall 2006 Prelim Exam – Power Problem #1 A delta connected generator provides a balanced 3 phase line-line voltage of 22,000 volts rms at 60 hertz. The load is a balanced 3 phase wye connected load, with each phase having an inductive impedance at 60 hertz of 10/_30 o ohms....
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## This note was uploaded on 09/23/2010 for the course ECE 0000 taught by Professor Ddaa during the Fall '10 term at Georgia Tech.

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Prelim_exam_sol_f06 - ECE PHD PRELIMINARY EXAMINATION...

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