DerekChiou_EE360N_Spring2010_Lecture3

DerekChiou_EE360N_Spring2010_Lecture3 - Lecture 3...

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© Derek Chiou Lecture 3: Microcoded Machines Prof. Derek Chiou University of Texas at Austin
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Test of size Announcements Have posted link to course notes in Course Documents on Blackboard Don’t forget to stop by and say “hi” during office hours M after class, T 3:30PM-4:30PM Or, make an appointment Will likely replace RAS 313A as a discussion room tomorrow or next week at the latest Will send email 09/28/10 © Derek Chiou : EE360N: Lecture 3 2
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Test of size 09/28/10 © Derek Chiou : EE360N: Lecture 3 3 Recap & Outline Recap ISAs depend on the underlying architecture Microcoded machines have nice properties Easy to understand, implement, add instructions Outline ISAs are highly dependent on microarchitecture Very complex instructions in microcoded machines Microcode Engine Control Improving Microcoded Machine Performance
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Test of size 09/28/10 © Derek Chiou : EE360N: Lecture 3 4 Microcode -> ISA Explosion ROM became cheap and fast Large microcode store possible Instructions easy to implement Doesn’t cost any additional hardware ISAs start to accumulate instructions can have a CWP instruction! Instructions quickly get out of hand Polynomial solve instruction in VAX Variable length instructions Addressing modes But, need to continue to support those instructions Which can be a pain later
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Test of size 09/28/10 © Derek Chiou : EE360N: Lecture 3 5 Eg., Memory Addressing Modes Direct addressing Full address encoded in instruction Limitations? Register Indirect Addressing Load DR, (SR) Load R0, (R1) Indexed Addressing Load DR, (SR + offset) Load R0, (R1 + 1) Base-Indexed Addressing Load DR, (SR1 + SR2) Load R0, (R2 + R3) Load DR, (SR1 + SR2 + offset) Load R0, (R1 + R2 + 1) Auto increment a register? Load DR, (SR1++) Load R0, (R1++) Load DR, (SR1 + SR2++ + offset) 10 20 30 40 0 1 -2 5 0 1 2 3 R0 R1 R2 R3 20 30 40 10 2 Memory Registers
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Test of size 09/28/10 © Derek Chiou : EE360N: Lecture 3 6 Review Exercise DR = MEM[SR1++] + MEM[++SR2] Regs Memory MAR MDR S shift A B ALU Control ALU has following ops A + B A + 1 A B
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Test of size 09/28/10 © Derek Chiou : EE360N: Lecture 3 7 Exercise Solution DR = MEM[SR1++] + MEM[++SR2]
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Test of size 09/28/10 © Derek Chiou : EE360N: Lecture 3 8 Exercise Solution A<-SR2 SR2,MAR<-A+1 B<-MEM A, MAR<-SR1 SR1<-A+1 A<-MEM DR<-A+B Be careful because SR1 and SR2 might be the same register.
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DerekChiou_EE360N_Spring2010_Lecture3 - Lecture 3...

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