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DerekChiou_EE360N_Spring2010_Lecture5

DerekChiou_EE360N_Spring2010_Lecture5 - Lecture 5 Memory...

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© Derek Chiou Lecture 5: Memory Prof. Derek Chiou University of Texas at Austin
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Test of size © Derek Chiou: EE360N: Lecture 5 2 Recap & Outline Recap Microcoded machines and memory Alternate ISA structures Simple pipelining A simple pipelined machine is an “unrolled” microcoded machine Outline Finish pipelining Memory SRAM/DRAM 09/28/10
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Test of size 09/28/10 © Derek Chiou: EE360N: Lecture 5 3 Why Pipeline? No wasted resources, no need to pipeline Share Resources Register file was sitting around doing nothing anyways Instead of an instruction consuming all of processor, consumes only part of processor (between pipeline registers) Increase Issue Rate Issue 1 instruction per cycle, instead of one every other cycle Increase overall performance Potentially increase clock rate Examples Track (wave pipeline) Disneyland (Space Mountain verses Star Tours) Car wash
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Test of size 09/28/10 © Derek Chiou: EE360N: Lecture 5 4 Definitions Instructions Per Clock Cycle (IPC) Average number of instructions executed per clock cycle Clock Cycles per Instruction (CPI) Average number of clock cycles per instruction Inverse of each other Dependent on application, ISA, micro-architecture, system DO PROBLEM 6
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Test of size 09/28/10 © Derek Chiou: EE360N: Lecture 5 5 Why Is Clock Rate Important? ClockCycle Time Inst s ClockCycle NumInst TotalTime * * =
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Test of size 09/28/10 © Derek Chiou: EE360N: Lecture 5 6 Why Is Clock Rate Important? ClockCycle Time Inst s ClockCycle NumInst TotalTime * * = CycleTime CPI NumInst TotalTime * * =
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Test of size 09/28/10 © Derek Chiou: EE360N: Lecture 5 7 Pipelining is Good, Can We Pipeline More? If ALU pipelined, can we issue twice as fast again?
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Test of size 09/28/10 © Derek Chiou: EE360N: Lecture 5 8 Pipelining is Good, Can We Pipeline More?
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