DerekChiou_EE360N_Spring2010_Lecture6

DerekChiou_EE360N_Spring2010_Lecture6 - Lecture 6: Memory...

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Lecture 6: Memory Part II Prof. Derek Chiou University of Texas at Austin © Derek Chiou 1
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Test of size Announcements z I will be out of town Feb 22 nd and Feb 23 rd z Class will be taught by Prof. Mattan Erez on the 22 nd z No office hours Monday/Tuesday, make appointment if you want to meet with me later in the week © Derek Chiou: EE360N: Lecture 6 2 2/8/2010
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Test of size Recap & Outline DO PROBLEM 9 z Recap z SRAM/DRAM z Started on using memory z Outline z Finish using memory z Interleaving z Start Caching (if we have time) © Derek Chiou: EE360N: Lecture 6 3 2/8/2010
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Test of size Memory Layout Across One Chip 16b 8 3b address 16 © Derek Chiou: EE360N: Lecture 6 4 2/8/2010
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Test of size Memory Layout Across Two Chips 16b 8 3b address High Low 8 8 © Derek Chiou: EE360N: Lecture 6 5 2/8/2010
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Test of size Memory Layout Across Four Chips 16b 8 3b address [15: 12] [7:4] [11:8] [3:0] 4 © Derek Chiou: EE360N: Lecture 6 6 2/8/2010
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Test of size Memories of Specific Generation store the same number of bits z Capacity = Height * Width * #Banks z SDRAM (1Gb) z 32M x 4 x 8 banks z 16M x 8 x 8 banks 8M 16 8 banks z 8M x 16 x 8 banks z As RAM output gets wider, RAM height gets shorter z Same number of bits per RAM! 32M 16M 8M © Derek Chiou: EE360N: Lecture 6 7 x4 x8 x16 2/8/2010
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Test of size Narrower RAMs Enable Greater Capacity Given Constant Total Width 2M x 4 8M x 16 3 © Derek Chiou: EE360N: Lecture 6 8 2/8/2010
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Test of size What If You Want More RAM Capacity? Go to smaller width RAMs x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 Any problems? Additional capabilities? © Derek Chiou: EE360N: Lecture 6 9 2/8/2010
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Test of size More Memory MAR 0 logic x8 x8 add CE CE WE WE x8 x8 CE CE WE WE 8 8 addr 8 8 © Derek Chiou: EE360N: Lecture 6 10 Any Problems? 2/8/2010
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Test of size Improved Performance? MAR 1 logic x8 x8 add CE CE WE WE x8 x8 CE CE WE WE 8 8 addr 8 8 Outstanding requests to both channels simultaneously © Derek Chiou: EE360N: Lecture 6 12 Outstanding requests to both channels simultaneously! 2/8/2010
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Test of size Improving Memory Throughput/Bandwidth using Interleaving/Banking z Latency z How long does it take to get from here to there DO PROBLEM 10 z and, maybe, back again z Throughput/Bandwidth z How many things can be done in some unit of time z Memory has long latency and relatively throughput z Early memory accesses could not be pipelined z when servicing one operation, others must wait How can throughput be increased? z z Interleaving/Banking z Banks now called channels because DRAM has banks internally © Derek Chiou: EE360N: Lecture 6 13 z RDRAM 2/8/2010
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Test of size Example: Banking in Cray-1 Example: Banking in Cray 1 Bank 0 Bank 1 Bank 2 Bank 15 MDR MAR MDR MAR MDR MAR MDR MAR Data bus Address bus CPU © Derek Chiou: EE360N: Lecture 6 14 2/8/2010
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Test of size Cray-1Banking Cray 1 Banking z CPU cycle = 12.5ns Memory cycle = 50ns z z If a memory bank conflict occurs, conflicting access and all operations behind it must wait for bank to and all operations behind it must wait for bank to become free z At most 4 banks used as once z Why 16 banks?
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