DerekChiou_EE360N_Spring2010_Lecture7

DerekChiou_EE360N_Spring2010_Lecture7 - Derek Chiou 1...

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Unformatted text preview: Derek Chiou 1 Lecture 7: Caches Prof. Derek Chiou University of Texas at Austin Test of size Derek Chiou: EE360N: Lecture 7 2 Announcements Computer Architecture Seminar Series Luca Carloni , Columbia System-Level Design of Embedded Platform Architectures Tuesday, Feb. 23, 3:30PM, ACES 2.302 Thursday Discussion Room changed from ENS 537 to ENS 109 Starting tomorrow Hopefully permanent 09/25/10 Test of size Survey of Lecture 6 The lecture was clear Percent AnsweredAgree68.182%Little improvement required31.818%Some improvement required0%Significant improvement required0% Unanswered 0% Question 2: Multiple Choice The lecture was well organized Percent AnsweredAgree86.364%Little improvement required13.636%Some improvement required0%Significant improvement required0% Unanswered 0% Question 3: Multiple Choice The pace of the lecture was: Percent AnsweredWay too fast0%A little too fast31.818%Just right63.636%A little too slow4.545%Way too slow0% Unanswered 0% Question 4: Essay The lecture was fine but I found a problem in homework 5 (Java Byte code). I could not understand the significance of that homework and what were we supposed to learn from it. The part about banking and overdriving the bus was glossed over too quickly. Do we need to know that? I believe it would be beneficial to know where each design we discuss fits in on a timeline mentioned in the first lecture. I became a little confused when you talked about the banks or "channels" and how the chip enable lines worked Would like it if we could talk a bit more about interleaving and banks. How exactly Hardware Alignment worked was a little unclear. The part with the alignment of the memory is a little confusing. Nothing as of now. None for this lecture. I thought we could have spend a bit more time on unaligned accesses and how they can be rectified using hardware and software. The lecture could've used more examples about specific uses of different memory conventions (least significant bit or most significant bit used for partitioning). Your little aside about processor binning brought back fond memories of my hardcore overclocking days. Also, I used to have an HP T1100 TabletPC with a 1Ghz Transmeta Crusoe. I would say it compared to a P4 at 1.5Ghz and certainly used much less juice at the time. It was a valiant effort and makes me wish that Intel wasn't the competition destroying behemoth that it is. I found the narrow RAM concepts confusing at the beginning. I found the Big Endian story amusing. Told my friends about it while we got pizza last night. They didnt agree unfortunately . Overall I found the memory concepts covered in this lecture less intuitive than the first lecture on memory....
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DerekChiou_EE360N_Spring2010_Lecture7 - Derek Chiou 1...

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