DerekChiou_EE360N_Spring2010_Lecture9

DerekChiou_EE360N_Spring2010_Lecture9 - Lecture 9: Virtual...

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© Derek Chiou 1 Lecture 9: Virtual Memory, Part I Prof. Derek Chiou University of Texas at Austin
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Test of size 2/17/2010 © Derek Chiou: EE360N: Lecture 9 2 Announcements Reminder: Will not be here next Monday and Tuesday Mattan Erez will be teaching No office hours Computer Architecture Seminar Series Luca Carloni , Columbia System-Level Design of Embedded Platform Architectures Tuesday, Feb. 23, 3:30PM, ACES 2.302
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Test of size 2/17/2010 © Derek Chiou: EE360N: Lecture 9 3 Recap & Outline Recap Caches III Outline Virtual Memory, Part I
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Test of size © Derek Chiou: EE360N: Lecture 8 4 Cache Control Instructions PowerPC dcbt: data cache block touch dcbtst: data cache block touch for store dcbz: data cache block zero dcbst: data cache block store Stores dirty data back to memory dcbf: data cache block flush 09/28/10
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Test of size © Derek Chiou: EE360N: Lecture 8 5 Victim Caches (Jouppi) Associative caches expensive Sometimes associativity necessary to get reasonable hit rate Some memory access patterns need associativity But perhaps on a small number Combine a large direct-mapped cache with a small fully-associative cache Fill fully-associative with conflicts from direct-mapped cache 09/28/10
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Test of size © Derek Chiou: EE360N: Lecture 8 6 Compiler/Code Optimizations: Part 1 How can this be improved? int addr_tag[NUM_SETS]; int lru_info[NUM_SETS]; int permit_tag[NUM_SETS]; 09/28/10
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Test of size © Derek Chiou: EE360N: Lecture 8 7 Compiler/Code Optimizations: Part 1 How can this be improved? int addr_tag[NUM_SETS]; int lru_info[NUM_SETS]; int permit_tag[NUM_SETS]; typedef struct { int addr_tag; int lru_info; int permit_tag; } cache_tag; Merging arrays 09/28/10
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Test of size © Derek Chiou: EE360N: Lecture 8 8 Compiler/Code Optimizations: Part 2 How can this be improved? for (j = 0; j < 100; ++j) { for (i = 0; i < 5000; ++i) { x[i][j] = 2 * x[i][j]; } } 09/28/10
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Test of size © Derek Chiou: EE360N: Lecture 8 9 Compiler/Code Optimizations: Part 2 How can this be improved? for (j = 0; j < 100; ++j) { for (i = 0; i < 5000; ++i) { x[i][j] = 2 * x[i][j]; } } for (i = 0; i < 5000; ++i) { for (j = 0; j < 100; ++j) { x[i][j] = 2 * x[i][j]; } } Loop interchange Depends on language: C/C++ is row-major , Fortran is column-major 09/28/10
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Test of size © Derek Chiou: EE360N: Lecture 8 10 Registers Versus Cache 09/28/10
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Test of size © Derek Chiou: EE360N: Lecture 8 11 Registers Versus Cache Registers and Cache (SRAM) are same technology 6T cross-coupled inverters with pass transistors Why differentiate? Could have 2MB register file! Number of ports On-chip SRAMs (cache) generally single ported Registers need at least 3, sometimes 10+ Address space Need to specify address in instruction 2MB/4B-per-word = 19b address per register * 3 = 57b for register specification alone! Access time Larger memories take longer to access 09/28/10
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Test of size 09/28/10 © Derek Chiou: EE360N: Lecture 8 12 Some Final Words on Caches “Cache size” generally only includes the data Total cache size (32KB means 32KB of data only ) Cache-line size (4B cache-line size means data only ) Does not include address tag, permission tag, etc.
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This note was uploaded on 09/23/2010 for the course EE 360n taught by Professor Staff during the Spring '08 term at University of Texas.

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DerekChiou_EE360N_Spring2010_Lecture9 - Lecture 9: Virtual...

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