DerekChiou_EE360N_Spring2010_Lecture10

DerekChiou_EE360N_Spring2010_Lecture10 - Lecture 10:...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Lecture 10: Virtual Memory, Part 2 Prof. Mattan Erez University of Texas at Austin © Derek Chiou 1 Test of size Recap and Outline Recap Virtual Memory Basics Address Translation Outline Finish Virtual Memory Basics Demand paging Virtual Memory Details Translation and protection Demand paging 2/22/2010 © Derek Chiou: EE360N: Lecture 10 2 Test of size Page Address Translation Where should page tables reside? special registers? ⇒ how many? effect on ISA, context-switching time main memory? ⇒ 100% memory reference overhead OS area user page number offset user page table origin of the page table user pages 2/22/2010 © Derek Chiou: EE360N: Lecture 10 3 Test of size Page Address Translation Where should page tables reside? special registers? ⇒ how many? effect on ISA, context-switching time main memory? ⇒ 100% memory reference overhead OS area user page number offset user page table origin of the page table user Translation Look-aside Buffer (TLB) pages a cache for page table entries to speed up the address translation (IBM, late 60’s) 2/22/2010 © Derek Chiou: EE360N: Lecture 10 4 Test of size Storage Hierarchies Storage is hierarchical in the order (away from the CPU) of increasing latency ti decreasing transfer bandwidth bi increasing natural unit of transfer xi ti < t i+1 bi ≥ b i+1 xi ≤ x i+1 increasing size si ⇒decreasing cost ci si ≤ s i+1, ci ≥ c i+1 Level 0: Registers Level 1: Caches Level 2: Main Memory (Primary Storage) Level 3: Disks (Secondary Storage) Level 4: Tape Backup (Tertiary Storage) 2/22/2010 © Derek Chiou: EE360N: Lecture 10 5 Test of size Hierarchical Storage Each level memoizes values stored at lower levels of storage to avoid full latency cost when accessing Effective Access time Ti = hi ti + (1- hi) ti+1 where hi is the ‘hit’ ratio, the probability of finding the desired data memoized at level i Given good locality of reference (i.e., small working set), hi ≈ 1 ⇒ Ti ≈ ti Balanced system gives the best of both world The performance of higher-level storage The capacity of lower-level low-cost storage. 2/22/2010 © Derek Chiou: EE360N: Lecture 10 6 Test of size Details: RAM verses Disk Disks much cheaper than RAM Disk currently about $0.10 GB (500GB for $50) DRAM currently $60 for 4GB DDR2 800MHz (9/28 Fry’s ad, AR) Disk 150 times cheaper! (exactly the same as last year) Disks (300GB Western Digital VelociRaptor SATA disk, 10KRPM) Disks much slower than RAM (www.tomshardware.com) 4.2ms read seek time 100MB/sec sustained rate 60ns – 100ns to read a block of memory 16bit * 800Mb/bit = 1.6GB/sec (one part) 64bit * 800Mb/bit = 6.4GB/sec 128bit * 800Mb/bit (interleaved) = 12.8GB/sec Memory DDR2 Disks 4-5 orders of magnitude longer latency, 16-25 times less bandwidth (assuming a single part, disks can be interleaved as well) © Derek Chiou: EE360N: Lecture 10 7 2/22/2010 Test of size Disk As Another Memory Hierarchy Level Disks huge compared to RAM Can we use disks as backing store to RAM? Make RAM look as big as disk but as fast as RAM? What caches did for RAM Do it manually or automatically? Relies on locality Memory is a Cache for Disk Important for sharing May be more than one program resident on computer at a time Aggregate program demands may be more than RAM © Derek Chiou: EE360N: Lecture 10 8 2/22/2010 Manual Technique: Overlaying to Run Programs Larger than Memory Test of size Programmer manages a part of secondary store by overlaying it repeatedly over primary store Assuming instruction can address all storage on the drum 40k bits main central store programmer keeps track of addresses in main memory and initiates an I/O transfer when program accesses addresses not in main memory automatic initialization of I/O transfers by software address translation 640k bits drum Brookner’s interpretive coding, 1960 First method too difficult, second too slow! 2/22/2010 © Derek Chiou: EE360N: Lecture 10 9 Test of size Demand Paging (Atlas 1962) “A page from secondary storage is brought into the primary storage whenever it is (implicitly) demanded by the processor.” Tom Kilburn Secondary (Drum) 32x6 pages Primary 32 Pages 512 words/page Central Memory Primary memory as a cache for secondary memory User sees 32 x 6 x 512 words of storage 2/22/2010 © Derek Chiou: EE360N: Lecture 10 10 Test of size Hardware Organization of Atlas Paging CPU Addr Decode PAR Mem Drum 1 page = 512 words 1 word = 48 bits PAR = Page Address Register one PAR per page frame (page addrs., lock bit, usage ) Additional ROM for programs, RAM for working area (not paged) 2/22/2010 © Derek Chiou: EE360N: Lecture 10 11 Test of size Atlas Demand Paging Scheme Page address compared against all 32 PAR’s match, normal access otherwise, page fault CPU Addr Decode PAR Mem Drum instruction interrupted, state saved input transfer initiated by consulting page table free page always kept PAR updated if no free page left, page out a page selection by usage learning program! selected page written to first empty page on drum page table updated to point to new location on drum © Derek Chiou: EE360N: Lecture 10 12 2/22/2010 Test of size Caching vs Demand Paging secondary memory CPU cache primary memory CPU primary memory caching cache entry cache block (~32B) cache miss (0.1% to 20%) cache hit (~1 cycle) cache miss (~100-300 cycles) a miss is handled in hardware 2/22/2010 demand paging page-frame page (~4k bytes) page miss (~.001%) page hit (~100-300 cycles) page miss(~15M cycles) a miss is handled either in software or hardware 13 © Derek Chiou: EE360N: Lecture 10 Test of size Abstract Virtual Memory •Only one process running at a time • Swapped in/out Process1 Process2 addr1 data Magic Virtual Memory Module (Memory Management Unit) addr2 data ProcessN •Permissions •Translate address •fetch from disk if necessary © Derek Chiou: EE360N: Lecture 10 14 2/22/2010 Test of size DETAILS 2/22/2010 © Derek Chiou: EE360N: Lecture 10 15 Test of size How To Translate? Base, bound and permission registers Assumptions and issues? Lookup virtual page in page table array Page_table[NUM_VIRTUAL_PAGES] Contains physical page number Permission information How do you deal with different jobs? Issues? © Derek Chiou: EE360N: Lecture 10 16 2/22/2010 Test of size How To Translate? Base, bound and permission registers Assumptions/issues? Contiguous physical address Contiguous virtual address Same permissions for entire space Lookup virtual page in page table array page_table[NUM_VIRTUAL_PAGES], num_pages Contains physical page number Permission information How do you deal with different jobs? page_table[NUM_JOBS][NUM_VIRTUAL_PAGES] num_pages[NUM_JOBS] Page_table is very large Virtual space must be contiguous (or waste space) © Derek Chiou: EE360N: Lecture 10 17 Issues? 2/22/2010 Test of size Where Do Page Tables Live? In Registers? Too many! VAX machine had 512B pages, 2GB virtual space per process 2GB/512B = (222 pages * 4B/page) = 16MB per process Multiple processes! In Physical memory? 16MB a lot of main memory per process for page tables! 64b machine of today, 8KB pages 264 /213 = 251 pages * 8B/page = a lot of RAM 8GB of RAM is 220 pages Not all processes use full virtual address space Can this help? © Derek Chiou: EE360N: Lecture 10 18 2/22/2010 http://www.ibm.com/developerworks/linux/library/l-memmod/ Test of size x86 (IA-32) Translation 32b How big is a page? Min VM Overhead? Min to address for 16B of data? Max? 32b 8b CR3 CR3, page directory and page table all physical addresses 10b Page Directory Page Table 10b 12b data VA 32b 2/22/2010 © Derek Chiou: EE360N: Lecture 10 19 Test of size What If You Run Out of Memory? 32b CR3 Page Directory 32b Page Table 8b data VA 10b 10b 12b 2/22/2010 © Derek Chiou: EE360N: Lecture 10 20 http://www.ibm.com/developerworks/linux/library/l-memmod/ Test of size What If You Run Out of Memory? 32b CR3 Page Directory 32b Page Table 8b data VA 10b 10b 12b Could page out data pages that aren’t being used Swapped out process? Page table entry has “memory/disk” bit, address in memory/disk Pointer in page directory needs to point to disk location! Page directory has “memory/disk” bit, address in memory/disk © Derek Chiou: EE360N: Lecture 10 21 Can page table be swapped out to disk? 2/22/2010 Test of size Another Real Example: VAX Virtual Memory VAX == Virtual Address Extension Extended PDP-11 32b address space, byte addressable Single family of machines that had different performance and amounts of memory but all ran the same programs 2/22/2010 © Derek Chiou: EE360N: Lecture 10 22 Test of size VAX View Of Memory PT 00 01 10 11 Virtual page num P0 Region P1 Region System space unused 232 Byte offset address (Reserved) System-wide space System Region 231 P1 (Control) Region Process space 230 P0 (Program) Region 0 2/22/2010 © Derek Chiou: EE360N: Lecture 10 23 Test of size VAX Page Tables One for each region (P0, P1, System) Why? Each page table stored sequentially in System Region 0 1 2 PTE for Page 0 PTE for Page 1 PTE for Page 2 P0 Base Reg L P0 Length (number of PTEs) L-1 PTE for Page L-1 PO/P1/System Length Registers used for ACV (access valid) checks PTE used for TNV (Table Not Valid) checks and translation © Derek Chiou: EE360N: Lecture 10 24 2/22/2010 Test of size PTE Entry What capabilites (read/write/execute) do I have? 20 V Protection field M For OS Physical frame num 0 valid Modified? How many pages of physical memory? How much physical memory? 25 2/22/2010 © Derek Chiou: EE360N: Lecture 10 Test of size VAX Protection Four protection modes User: user programs, compilers, editors, games, etc. Supervisor: shell Executive: file subsystem Kernel: scheduling, I/O operations, memory management User < Supervisor < Executive < Kernel None < Read < Write Static priority Access modes 2/22/2010 © Derek Chiou: EE360N: Lecture 10 26 Test of size Abstract VAX Virtual Memory 00 Virtual page num Byte offset VA P0LR < 1. VPageNum < P0LR? Else ACV fault! 2. Read appropriate PTE PFN PFN PFN PFN P0BR V Protection Page table V Protection V Protection V Protection 3. Allowed access? Else ACV fault! 4. Page resident? Else TNV fault! OK! Construct physical address V Protection PFN Byte offset 2/22/2010 © Derek Chiou: EE360N: Lecture 10 27 Test of size Abstract Virtual Memory Virtual Space P0[0] P0 Region P0[1] P0[2] NOT TO SCALE Physical Memory P0[2] Page Tables P 0 BR 0 1 1 P0LR P1[1] 0 0 1 0 P0[1] P 1 BR P1 Region P1[1] P1[0] S [0] S [1] S [2] S[2] P 1LR 7FFFFFFF 80000000 S[0] System Region 1 0 1 0 SBR SLR 8FFFFFFF 2/22/2010 Where Do Page Tables Reside? What sort of address is P0BR? What sort of address is SBR? © Derek Chiou: EE360N: Lecture 10 28 Test of size Page Tables in Virtual Memory! Page Tables P0[0] P0 Region P0[1] P0[2] 0 1 1 P0[2] P1[1] P0[1] P1 Region P1[1] P1[0] 0 0 1 0 P0BR System Region P1BR •Use same paging mechanism for page tables! •Page page tables, don’t waste memory 8FFFFFFF •But, how do we find physical location? 29 2/22/2010 © Derek Chiou: EE360N: Lecture 10 User Page Tables Have System Virtual Memory Addresses Virtual memory P0[0] P0 Region P0[1] P0[2] 0 1 1 Test of size Page Tables Physical memory P0 PT P0[2] P1[1] P0[1] P1 Region P1[1] P1[0] 0 0 1 0 P1 PT P 0BR System Page Table 0 0 1 0 0 1 SBR System Region P 1BR What sort of address is SBR? 8FFFFFFF 2/22/2010 © Derek Chiou: EE360N: Lecture 10 30 Test of size Another View: Collapsed Page Tables P0[0] P0 Region P0[1] P0[2] P0[2] P1[1] P0[1] P1 Region P1[1] P1[0] System Page Table 0 0 1 0 0 1 SBR P0BR System Region P1BR 8FFFFFFF 2/22/2010 © Derek Chiou: EE360N: Lecture 10 31 Test of size Translation Overview A = X implies ld X Need to find the PTE of page containing X (PTE(X)) Use P0BR to determine virtual address of PTE(X) Page Tables P0[0] P0 Region P0[1] P0[2] P0[ 2] P1[ 1] P0[ 1] P1 Region P1[1] P1[0] System Page Table 0 0 1 0 0 1 SBR P0BR System Region Read PTEX to determine physical page/permissions P1BR 8FFFFFFF Check permissions Create physical address Read X using physical address © Derek Chiou: EE360N: Lecture 10 32 2/22/2010 Test of size Translation Overview A = X implies ld X Need to find the PTE of page containing X (PTE(X)) Use P0BR to determine virtual address of PTE(X) Page Tables P0[0] P0 Region P0[1] P0[2] P0[ 2] But, PTE(X) is virtual address! Use SBR to determine physical address of PTE(PTE(X)) Read PTE(PTE(X)) to determine physical page/permissions of PTE(X) Check permissions Create physical address P1[ 1] P0[ 1] P1 Region P1[1] P1[0] System Page Table 0 0 1 0 0 1 SBR P0BR Read PTE(X) to determine physical page/permissions System Region P1BR Check permissions Create physical address 8FFFFFFF Read X using physical address 2/22/2010 © Derek Chiou: EE360N: Lecture 10 33 Test of size Step-by-Step: What Is Being Computed? Page Tables VA of X x4 P0[0] P0 Region P0[1] P0[2] P0[2] P1[1] P0[1] P1 Region P1[1] P1[0] System Page Table 0 0 1 0 0 1 SBR + PxBR P0BR System Region P1BR x4 + SBR paddr paddr paddr V Per V Per X 8FFFFFFF PFN PFN 2/22/2010 © Derek Chiou: EE360N: Lecture 10 34 Test of size Step-by-Step: What Is Being Computed? Page Tables A = X; VA of X x4 + PxBR P0[0] P0 Region P0[1] P0[2] P0[2] P1[1] P0[1] P1 Region P1[1] P1[0] System Page Table 0 0 1 0 0 1 SBR VA of PTE of Page containing X (in System Region) P0BR System Region P1BR 8FFFFFFF x4 + SBR paddr paddr paddr 2/22/2010 © Derek Chiou: EE360N: Lecture 10 System Region PTE V Per V Per X PFN PTE of page containing X PFN 35 Specific Example: Step-by-Step 9b virtual address, 8 physical pages 00 VA of X 01 01010 P0BR 100100000 Test of size x4 + VA of PTE of Page containing X (in System Region) 10 01 00100 SBR 000000000 x4 + SBR 000000100 System Region PTE V Per V Per X 001 PTE of page containing X 001 00100 000 000 01010 2/22/2010 © Derek Chiou: EE360N: Lecture 10 36 ...
View Full Document

Ask a homework question - tutors are online