22 Sequential-1 - Sequential Logic Sequential Circuits-...

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Sequential Logic
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Sequential Circuits- outputs depend on previous as well as current inputs. Circuits have states . Ex: FSM/Pipelines
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Latches and Flip flops two commonly used sequencing elements. Latch is transparent when the clock is high and opaque when clock is low. Flip-flop is an edge triggered device that copies Input to Output on the rising edge of the clock and ignores Input at all other times.
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Static Sequencing
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Timing metrics of sequential circuits setup time: the time the data input must be valid before the clock transition hold time: the time the data input is valid after the clock transition. Propagation delay : assuming setup time and hold time are met data at the input copied to the output after worst case propagation delay.
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Timing Diagrams.
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pd - Logic propagation delay t setup - data input must be stable for some window around the rising edge of the flipflop t hold – should not change again until a hold time after the clock edge. t
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This note was uploaded on 09/24/2010 for the course EEE MEL G621 taught by Professor Gurunarayanan during the Fall '08 term at Birla Institute of Technology & Science, Pilani - Hyderabad.

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22 Sequential-1 - Sequential Logic Sequential Circuits-...

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