23 Sequential-2 - 1 Q D 0 clk D - LATCH D D Widely used in...

Info iconThis preview shows pages 1–27. Sign up to view the full content.

View Full Document Right Arrow Icon
clk Q D 0 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 2
D - LATCH
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
D
Background image of page 4
D Widely used in standard cell library
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
C 2 MOS Latch
Background image of page 6
clk Q M D 0 1 clk Q 1 0
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 8
Max Delay Constraints T c t pcq + t pd + t setup
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Min – delay constraints t cd ≥ t hold - t ccq
Background image of page 10
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 12
A B Case I: D = 0, CLK = 0 D = 0 => B = 1 CLK = 0 => R =1, S = 1 B = 1, S = 1 => A = 0 ASRB = 0111 SR = 11 => No change •CLK = 0 => R =1, S = 1 •D = 1, R = 1 => B = 0 •B = 0, S = 1 => A = 1 •ASRB = 1110 •SR = 11 => No change
Background image of page 13

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
In case I make CLK=1 i.e., ASRB=0111 D=0 => B=1 B=1, S=1 => A=0 A=0 => S=1 S=1,B=1,CLK=1 => R=0 SR=10 => RESET ASRB=0101 Only R has changed here after one gate delay. If D changes after R has stabilized there will be no effect on output. This is Hold Time. A B
Background image of page 14
In case I make CLK=1 i.e., ASRB=0111 D=0 => B=1 B=1, S=1 => A=0 A=0 => S=1 S=1,B=1,CLK=1 => R=0 SR=10 => RESET ASRB=0101 Only R has changed here after one gate delay. If D changes after R has stabilized there will be no effect on output. This is Hold Time . A B
Background image of page 15

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
A B Case II: D = 1, CLK = 0 CLK = 0 => R =1, S = 1 D = 1, R = 1 => B = 0
Background image of page 16
Background image of page 17

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 18
Background image of page 19

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 20
Background image of page 21

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 22
Background image of page 23

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 24
Background image of page 25

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 26
Background image of page 27
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 27

23 Sequential-2 - 1 Q D 0 clk D - LATCH D D Widely used in...

This preview shows document pages 1 - 27. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online