27 clock - In Combinational Logic Output QRegisters D CLK...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
Combinational Logic Registers In Output Q D CLK
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Timing Definitions t CLK t D t c - q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ t su - setup time Minimum clock required for proper operation of the seq circuit. T t c-q +t plogic +t s u , tcd,register + tcd,logic thold Data at D input is coped to Q output t c-q
Background image of page 2
In Q 0 Q 1 Clk 100 Sequence of Operation Cascaded Flipflops and Setup/Hold/Propagation Delays Shift Register New value to first stage while second stage obtains current value of first stage Correct Operation, assuming positive edge triggered FFs IN CLK Q0 Q1 D C Q Q D C Q Q
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Synchronous Logic Timing (with registers) Combinational Logic R 1 R 2 C in C out Out In CLK Minimum cycle time: T > t c-q + t su + t logic T depends on latch/register/ff parameters! tclk1 tclk2 Hold time of the destination register must be shorter than the minimum propagation Delay through network. thold < tcq + tlogic
Background image of page 4
Clock Skew: Spatial variation in arrival time of a clock transition on an IC.
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 6
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 20

27 clock - In Combinational Logic Output QRegisters D CLK...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online