combinational logic I - (nMOS Depletion load) Two input NOR...

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Unformatted text preview: (nMOS Depletion load) Two input NOR Gate. VOH: VA and VB lower than corresponding driver threshold voltage driver transistors off. I D,load = (kn.load/2)([2 |V T,load (V OH ) | .(V DD-V OH )-(V DD-V OH ) 2 ]) = 0 V OH = V DD . V OL : V A = V OH V B = V OL V A = V OL V B = V OH V A = V OH V B = V OH V OL : V A = V OH V B = V OL V A = V OL V B = V OH V A = V OH V B = V OH Case (i) and (ii) – nMOS depletion load inverter Assuming threshold voltages of the two enhancement type driver are identical k R = k driver.A / k load (A is ON) k R = k driver.B /k load (B is ON) Output voltage in both the cases is V OL = V OH – V T0-((V OH-V T0 ) 2 –(k load /k driver ).|V T.load (V OL ) | 2 ) 1/2 If (W/L)A = (W/L)B then VOL same in both the cases. Case (iii) I D.load = I D.driverA + I D.driverB k R = (k driver.A +k. driver.B )/k load. Equivalent driver to load ratio for the NOR structure is ( k n.driver ’ [(W/L) A + (W/L) B ])/(k n.load ’ (W/L) load ) V OL = V OH – V TO- [(V OH-V TO ) 2-(k load /(k driver.A +k driver.B )). | V Tload (VOL) | 2 ] 1/2 Worst case VOL happens for case (i) and (ii) Determine driver to load ratio using V OL of case (i) or (ii) Then set k driver.A = k driver.B = k R k load NOR Structure with multiple inputs I D = Σ I D,k k(on) (W/L) equ = Σ (W/L) k k(on) Two-input NAND Gate...
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This note was uploaded on 09/24/2010 for the course EEE MEL G621 taught by Professor Gurunarayanan during the Fall '08 term at Birla Institute of Technology & Science, Pilani - Hyderabad.

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combinational logic I - (nMOS Depletion load) Two input NOR...

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