Int Prasitics - Interconnect Parasitic Output load...

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Interconnect Parasitic

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Output load classified as three components. - Internal parasitic capacitances of transistors - Interconnect (line) capacitances - Input capacitances of fanout gates. Interconnection in sub micron circuit causes problems.

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Chip designers need efficient means for - estimating interconnect parasitics - Simulating transient effects.
Interconnect Capacitance Estimation. Each interconnection line is a three dimensional structure in metal/or polysilicon, with significant variation in shape, thickness and vertical distance from ground plane ( substrate) ; surrounded by number of other lines.

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Interconnect Capacitance Estimation. Each interconnection line is a three dimensional structure in metal/or polysilicon, with significant variation in shape, thickness and vertical distance from ground plane ( substrate) ; surrounded by number of other lines. wire has length l width w and thickness t Runs parallel to chip Surface separated by Dielectric layer by ‘h’ Cpp. = ( ε /h)(W.L)
Capacitance between the sidewalls of the wire and substrate Fringing field significantly increases the total capacitance. Fringing field is a function of (t/h), (w/h), (w/l).

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C = ε [ (w- t/2)/h +2 π / (ln(1+2h/t +{2h/t(2h/t+2)} 1/2 ) ] for w t/2 C = ε [w/h + π ( 1- 0.0543. t/2h)/ (ln (1+2h/t + (2h/t) 1/2 (2h/t +2) + 1.47] for w < t/2 Developed by Yuan and Trick.
. Geometry to be taken into account for every portion of wire. Chip manufactures provide area capacitance and perimeter capacitance.

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This note was uploaded on 09/24/2010 for the course EEE MEL G621 taught by Professor Gurunarayanan during the Fall '08 term at Birla Institute of Technology & Science, Pilani - Hyderabad.

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Int Prasitics - Interconnect Parasitic Output load...

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