MOS Switching Char2 - PHL = Cload /kn(VDD-VT,n)...

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
τ PHL = C load /k n (V DD -V T,n ) [(2V T,n /(V DD -V T,n )) + ln((4(V DD -V T,n )/V DD ) -1)]
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
τ PLH = C load /k P (V DD -|V T,P |) [(2 |VT,P| /(V DD -|V T,P |)) + ln((4(V DD -|V T,P |)/V DD ) -1)] For τ PLH = τ PHL V T,n = | V T,p | and k n = k p ( or W P /W N = µ n / µ p )
Background image of page 2
Load capacitance made of Intrinsic and extrinsic components
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Inverter Design based on timing delay specifications – fundamental issue in digital circuit design Transistor sizes found from delay requirements must also meet other design criteria- noise margin, power dissipation etc.
Background image of page 4
Inverter Design Device Parameters: µ n C ox = 120 µ A/V 2 , µ p C ox = 120 µ A/V 2 L = 0.6 µ m for both nMOS and pMOS devices. V T0,n = 0.8V, V T0,p = -1.0V, W min = 1.2 µ m Inverter Specifications: V th = 1.5V, V DD = 3V τ PLH 0.2nS and τ PHL 0.15nS A Falling delay of 0.35nS for an output transition of 2V to 0.5V C load = 300pF.
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Cload = Cgd,n(Wn) + Cgd,p(Wp) + Cdb,n(Wn) + Cdb,p(Wp) + Cint +Cg Determination of device dimensions to satisfy delay constraints – any
Background image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 24

MOS Switching Char2 - PHL = Cload /kn(VDD-VT,n)...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online