MIT6_012s09_project

MIT6_012s09_project - MIT OpenCourseWare http:/ocw.mit.edu...

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MIT OpenCourseWare http://ocw.mit.edu 6.012 Microelectronic Devices and Circuits Spring 2009 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms .
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Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.012 Microelectronic Devices and Circuits Spring 2009 Design Project _____________________________________________________________ This project may be worked on in groups of two. If you choose to work with a partner, turn in one report for both partners. The design process is long – start working early. 1 The Optical Converter Information can be encoded and transmitted optically. Such a data transmission system requires a decoding receiver that converts the information contained in the intensity of transmitted photons into useful electrical signals understandable by digital processors. You will be designing a converter from photons to a pulse width modulated signal to be used as the first stage of a four-state optical receiver. Our converter will generate pulses of four different widths in time, corresponding to the four light intensity levels the receiver detects. We will design for a 200MHz receiver system clock speed. The four pulses must be wide enough to allow for several clock cycles to complete in one pulse, and sufficiently distinct in width from each other for each of the four pulses to be differentiated by the next stage of the receiver, which counts the number of clock cycles within a pulse. The converter should be designed in three stages: 1. Stage 1 detects the incoming photon intensity and converts it into a current signal. A photodiode is a device that passes a current that is directly proportional to the detected light intensity. This current is used in the generation of two voltage steps, where the time delay between the two steps is a function of the photodiode current. 2. Stage 2 converts the time delayed voltage steps to a single pulse, whose pulse width is the time delay between the two outputs from Stage 1. 3. Stage 3 is an output buffer that is designed to drive a 5pF load capacitance. As electronics trend ever smaller and more portable, die area has become an increasingly important design parameter for circuit designers. In this project, we will focus our design efforts on minimizing total gate area while preserving desired functionality.
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2 Implementation 2.1 STAGE 1 We will model the photodiode in our circuit as an ideal four level current source that sources I light = 0μA, 1μA, 2μA, and 3μA, with 0μA corresponding to a completely dark input. A bias current source of I bias = 2μA is placed in parallel with the photodiode. The two current sources sum and drive the capacitance seen at node N1, which will be the sum of gate capacitances of inverters 1 and 2. An ideal voltage controlled switch connects N1 to ground. When the switch is closed, node N1 sees a direct path to ground. When the switch is open, the current sources charge the capacitances at N1, producing a
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This note was uploaded on 09/24/2010 for the course EE 6.012 taught by Professor Charlessodini during the Spring '08 term at MIT.

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MIT6_012s09_project - MIT OpenCourseWare http:/ocw.mit.edu...

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