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MIT6_012s09_lec20

# MIT6_012s09_lec20 - MIT OpenCourseWare http/ocw.mit.edu...

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MIT OpenCourseWare http://ocw.mit.edu 6.012 Microelectronic Devices and Circuits Spring 2009 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms .

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Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages Outline Common-drain amplifier Common-gate amplifier 6.012 Spring 2009 1 Reading Assignment: Howe and Sodini; Chapter 8, Sections 8.7-8.9
1. Common-drain amplifier V DD signal source v s V BIAS R S signal load + i SUP R L v OUT - A voltage buffer takes the input voltage which may have V SS a relatively large Thevenin resistance and replicates the voltage at the output port, which has a low output resistance Input signal is applied to the gate Output is taken from the source To first order, voltage gain 1 Input resistance is high Output resistance is low Effective voltage buffer stage v gate ↑⇒ i D cannot change v source Source follower How does it work? 6.012 Spring 2009 2

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Biasing the Common-drain amplifier V DD signal source v s V BIAS R S V SS signal load + i SUP R L v OUT - V SS± Assume device in saturation; neglect R S and R L ; neglect CLM ( λ = 0) Obtain desired output bias voltage Typically set V OUT to”halfway” between V SS and V DD . Output voltage maximum V DD -V DSsat Output voltage minimum set by voltage requirement across I SUP . V BIAS = V GS + V OUT V GS = V Tn ( V SB ) + I SUP W 2 L μ n C ox 6.012 Spring 2009 3
Small-signal Analysis Unloaded small-signal equivalent circuit model: D G g m v gs r S v in + r oc v out - - ± v in = v gs + v out v out = g m v gs ( r o // r oc ) Then: A vo = g m g m + 1 r o // r oc 1 + - v gs + - v in + - v out g m v gs r o //r oc 6.012 Spring 2009 4

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Input and Output Resistance Input Impedance : R in = Output Impedance: + - v gs + - v in g m v gs r o //r oc + - v t i t i t R S
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