MIT6_012s09_lec12

MIT6_012s09_lec12 - MIT OpenCourseWare http://ocw.mit.edu...

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Unformatted text preview: MIT OpenCourseWare http://ocw.mit.edu 6.012 Microelectronic Devices and Circuits Spring 2009 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms . Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline • NMOS inverter with resistor pull-up –The inverter • NMOS inverter with current-source pull-up • Complementary MOS (CMOS) inverter • Static analysis of CMOS inverter Reading Assignment: Howe and Sodini; Chapter 5, Section 5.4 6.012 Spring 2009 Lecture 12 1 1. NMOS inverter with resistor pull-up: Dynamics • C L pull-down limited by current through transistor – [shall study this issue in detail with CMOS] • C L pull-up limited by resistor (t PLH ≈ RC L ) • Pull-up slowest V IN : LO HI V IN : HI LO V OUT : HI LO V OUT : LO HI V DD C L R V DD C L R pull-down pull-up 6.012 Spring 2009 Lecture 12 2 1. NMOS inverter with resistor pull-up: Inverter design issues Noise margins ↑ ⇒ |A v | ↑⇒ • R ↑ ⇒ |RC L | ↑⇒ slow switching • g m ↑ ⇒ |W| ↑⇒ big transistor – (slow switching at input) During pull-up we need: • High current for fast switching • But also high incremental resistance for high noise margin. 6.012 Spring 2009 Lecture 12 3 Trade-off between speed and noise margin. 2. NMOS inverter with current-source pull-up • High current throughout voltage range v SUP > 0 • i SUP = 0 for v SUP ≤ 0 • i SUP = I SUP + v SUP / r oc for v SUP > 0 • High small-signal resistance r oc. Equivalent circuit models : I—V characteristics of current source: i SUP I SUP v SUP 1 r oc v SUP i SUP + _ I SUP r oc i SUP v SUP + _ r oc large-signal model small-signal model 6.012 Spring 2009 Lecture 12 4 NMOS inverter...
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This note was uploaded on 09/24/2010 for the course EE 6.012 taught by Professor Charlessodini during the Spring '08 term at MIT.

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MIT6_012s09_lec12 - MIT OpenCourseWare http://ocw.mit.edu...

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