designproject - Spring 2007 6.720J/3.43J Integrated...

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Spring 2007 6.720J/3.43J Integrated Microelectronic Devices Prof. J. A. del Alamo Design Problem Gate Material Options for Deep-Submicron CMOS Technology for High-Performance Microprocessor Applications April 27, 2007± Due: May 11, 2007 at lecture± 1. Introduction In modern scaled-down CMOS, the gate material of choice for the n-channel MOSFET is n + -polySi, while that of the p-channel MOSFET is p + -polySi. As device scales down, a number of concerns with this approach are being raised. First, the resistance of the gate is increasing to the point that is starting to introduce a signi²cant delay on the ability of wide devices to drive large interconnect lines. The resistance of the gate goes up in scaled-down devices because the gate length is getting shorter and because of edge effects, that is, narrow gate lines have a sheet resistance that is higher than wide gate lines. The second problem with poly-Si gates is that even though they are heavily doped, a non-negligible fraction of the available gate voltage drops at its interface with the oxide. With the voltage budget and the oxide thickness going down, the fraction of the voltage lost in the gate is becoming signi²cant. This phenomenon is called “poly depletion”. A third concern is the diffusion of dopants from the gate to the channel during device fabrication. With a thick gate oxide, this is effectively suppresed. As the gate oxide is getting thinner, avoiding gate dopant diffusion through the gate oxide to the channel is starting to impose serious processing constraints that ultimately detract from performance. All these problems point at the need to examine alternate gate materials for future deep-submicron generations of scaled-down CMOS. An attractive approach is a refractory metal gate. A metalic gate has a very small resistance with minimum RC time constant. A metal gate does not develop any surface potential and does not detract from the voltage applied to the inversion layer. Finally, since dopants are absent from a metal gate, dopant diffusion through the gate oxide is eliminated. There are certainly many issues to be worked out: process compatibility, ²ne-line de²nition, and reliability, among others. The constraints imposed on a new gate technology are so severe that it would represent a great simpli²cation if a single gate technology, as opposed to two (one for the n-MOSFET and another one for the p-MOSFET), is to be developed. In a uni²ed gate approach, the gate should have a work function that lines up closely with the middle of the Si bandgap. This is likely to result in the Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007. MIT OpenCourseWare (, Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].
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This note was uploaded on 09/24/2010 for the course EECS 6.720J taught by Professor Jesúsdelalamo during the Spring '07 term at MIT.

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designproject - Spring 2007 6.720J/3.43J Integrated...

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