rob - - Design : (Tomasulo) ReOrder Buffer - entity : ROB -...

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-- -- Design : (Tomasulo) ReOrder Buffer -- entity : ROB -- Project : Tomasulo Processor -- Script : Tomasulo 2k9 team (modified by Omair A. Rahman). -- Company : University of Southern California -- Date : July 03, 2009 ----------------------------------------------------------------------------- -- ----------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.robspecs.all; entity rob is port(--inputs-- clk :in std_logic; reset :in std_logic; cdb_valid :in std_logic; --CDBValid cdb_robtag :in std_logic_vector(4 downto 0); --ROBTag cdb_data :in std_logic_vector(63 downto 0); --CDBData cdb_br :in std_logic; --Branch cdb_deci :in std_logic; --BranchTaken mem_wri :in std_logic; --MemWritten mem_exc :in std_logic; --MemException dis_br_addr :in std_logic_vector(31 downto 0); --BranchAddr dis_pc :in std_logic_vector(31 downto 0); --PC dis_br_pred :in std_logic; --BrnchPredict dis_br :in std_logic; --BranchBit dis_rdaddr :in std_logic_vector(4 downto 0); --RdAddr dis_instype :in std_logic; --InstrType dis_insvalid :in std_logic; --InstrValid dis_rsaddr :in std_logic_vector(4 downto 0); --RsAddr dis_rtaddr :in std_logic_vector(4 downto 0); --RtAddr --outputs-- rob_top :out std_logic_vector(4 downto 0); --RobTopPointer flush :out std_logic; --RobFlush
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depth :out std_logic_vector(4 downto 0); --RobDepth swflush :out std_logic; --SWFlush swaddr :out std_logic_vector(31 downto 0); --SWAdd mem_write :out std_logic; --MemWrite mem_addr :out std_logic_vector(31 downto 0); --MemAddr mem_data :out std_logic_vector(31 downto 0); --MemData reg_write :out std_logic; --Regwrite reg_addr :out std_logic_vector(4 downto 0); --RegAddr reg_data :out std_logic_vector(31 downto 0); --RegData rob_bottom :out std_logic_vector(4 downto 0); --BottomPointer rob_full :out std_logic; --ROBFull rob_outcome :out std_logic; --ROBBranchOutcome br_add :out std_logic_vector(31 downto 0); --BrnchAdd br_update :out std_logic; --BrnchUpdate br_bits :out std_logic_vector(2 downto 0); --BrnchBits rsdatavalid :out std_logic; --RsDataValid rtdatavalid :out std_logic; --RtDataValid rsdata :out std_logic_vector(31 downto 0); --RsData rtdata :out std_logic_vector(31 downto 0); --RtData rstagvalid :out std_logic; --RsTagValid rttagvalid :out std_logic; --RtTagValid rstag :out std_logic_vector(4 downto 0); --RsTag rttag :out std_logic_vector(4 downto 0) --RtTag ); end rob; architecture rob_arch of rob is signal cond_in_branch : std_logic; signal the_tag,the_tag_rt : std_logic_vector(4 downto 0); signal tag_found, tag_found_rt : std_logic; signal top, bottom,internal_depth: std_logic_vector(4 downto 0); signal act_pc: std_logic_vector(31 downto 0); signal topy, bottomy, checker : std_logic_vector(5 downto 0); signal full, commit, flush_rob : std_logic;
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signal rob_tag: rob_5bit_array; signal rob_regwrite,rob_valid,rob_comp,rob_br,rob_type,rob_br_pred : rob_bitfield_array;
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rob - - Design : (Tomasulo) ReOrder Buffer - entity : ROB -...

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