reg_file

reg_file - - Design : Register File (Dispatch Unit) -...

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------------------------------------------------------------------------------- -- -- Design : Register File (Dispatch Unit) -- Project : Tomasulo Processor -- Entity : register_file -- Author : Prashesh Patel -- Company : University of Southern California -- Last Updated : June 28, 2008 ------------------------------------------------------------------------------- -- -- Description : 32 wide 32 deep register file. $0 is never wriiten during circuit -- operation. So it is rplaced with hard wired 0s by synthesis tool -- It has 2 read port and 1 write port. Reading is asynchronous and -- writing is synchronous ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------------------------------------------------- -------------------------- entity register_file is generic(
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This note was uploaded on 09/26/2010 for the course EE 596 taught by Professor Antonioortega during the Fall '08 term at USC.

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reg_file - - Design : Register File (Dispatch Unit) -...

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