Lsq - CHECKED AND MODIFIED BY PRASANJEET-UPDATED ON Design Load Store Queue Project Tomasulo Processor Author Rohit Goel Company University of

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Unformatted text preview: -- CHECKED AND MODIFIED BY PRASANJEET---------------------------------------------UPDATED ON: 7/14/09------------------------------------------------------------------------------------------------------------------------------ Design : Load - Store Queue-- Project : Tomasulo Processor -- Author : Rohit Goel -- Company : University of Southern California ------------------------------------------------------------------------------------- File : lsq.vhd-- Version : 1.0------------------------------------------------------------------------------------- Description : The load store queue stores lw - sw instructions and dispatches -- instructions to the issue block as and when they are ready to be -- executed. Higher priority is given to instructions which has been -- in the queue for a longer period------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;--use ieee.std_logic_unsigned.all;-- Entity declaration entity lsq is port (-- Global Clk and Reset Signals clk : in std_logic ; reset : in std_logic ;-- Information to be captured from the CDB (Common Data Bus) CdbTag : in std_logic_vector(4 downto 0) ; CdbData : in std_logic_vector(31 downto 0) ; CdbValid : in std_logic ;-- Information from the Dispatch Unit DisOpcode : in std_logic ; DisRsData : in std_logic_vector(31 downto 0) ; DisAddr : in std_logic_vector(15 downto 0 ) ; DisRsDataValid : in std_logic ; DisRtData : in std_logic_vector(31 downto 0) ; DisRtTag : in std_logic_vector(4 downto 0) ; DisRsTag : in std_logic_vector(4 downto 0 ) ; DisRtDataValid : in std_logic ; DisRdTag : in std_logic_vector(4 downto 0) ; DisEnable : in std_logic ; IssuequeFull : out std_logic ;-- Interface with the Issue Unit IssuequeReady : out std_logic ; IssuequeOpcode : out std_logic ; IssuequeRdTag : out std_logic_vector(4 downto 0) ; IssuequeAddr : out std_logic_vector(31 downto 0) ; IssuequeData : out std_logic_vector(31 downto 0) ; IssueblkDone : in std_logic;-- Interface with ROB RobFlush : in std_logic; RobTopPointer : in std_logic_vector ( 4 downto 0 ) ; RobDepth : in std_logic_vector ( 4 downto 0 ) ; FlushSw : in std_logic ; FlushSwTag : in std_logic_vector ( 4 downto 0 ) ) ; end lsq;-- Architecture begins here architecture behave of lsq is-- Component declarations component Lsquectrl port (-- Global Clk and Reset Signals clk : in std_logic ; reset : in std_logic ;-- cdb interface CdbTag : in std_logic_vector(4 downto 0) ; CdbValid : in std_logic ;-- dispatch / issue unit interface DisEnable : in std_logic ; IssueblkDone : in std_logic ;------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ address calc section Opcode : in std_logic_vector(3 downto 0); -- '1' indicates lw and '0' is a sw AddrReadyBit : in std_logic_vector(3 downto 0); -- '1' indicates...
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This note was uploaded on 09/26/2010 for the course EE 596 taught by Professor Antonioortega during the Fall '08 term at USC.

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Lsq - CHECKED AND MODIFIED BY PRASANJEET-UPDATED ON Design Load Store Queue Project Tomasulo Processor Author Rohit Goel Company University of

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