issuequectrl

issuequectrl - - CHECKED AND MODIFIED BY PRASANJEET...

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-- CHECKED AND MODIFIED BY PRASANJEET ------------------------------------------- --UPDATED ON: 7/9/09 ------------------------------------------- ------------------------------------------------------------------------------- -- -- Design : Issue Cntrl -- Project : Tomasulo Processor -- Author : Rohit Goel -- Company : University of Southern California -- ------------------------------------------------------------------------------- -- -- File : issuequectrl.vhd -- Version : 1.0 -- ------------------------------------------------------------------------------- -- -- Description : The Issue control controls the Issuque ------------------------------------------------------------------------------- --Library declaration library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; -- Entity declaration entity issuequectrl is port ( -- Global Clk and Reset Signals clk : in std_logic ; reset : in std_logic ; -- cdb interface CdbTag : in std_logic_vector(4 downto 0) ; CdbValid : in std_logic ; -- ROB Interface RobFlush : in std_logic ; RobTopPointer : in std_logic_vector (4 downto 0 ) ; RobDepth : in std_logic_vector (4 downto 0 ) ; -- dispatch / issue unit interface DisEnable : in std_logic ; IssueBlkDone : in std_logic ; -- shift register inputs InstructionValidBit : in std_logic_vector(3 downto 0); -- '1' indicates instruction is valid in the buffer RsDataValidBit : in std_logic_vector(3 downto 0); -- '1' indicates rs data is valid in the buffer RtDataValidBit : in std_logic_vector(3 downto 0); -- '1' indicates rt data is valid in the buffer Buffer0RsTag : in std_logic_vector(4 downto 0); --From each entry of the issue queue, you have space of four entries
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Buffer1RsTag : in std_logic_vector(4 downto 0); Buffer2RsTag : in std_logic_vector(4 downto 0); Buffer3RsTag : in std_logic_vector(4 downto 0); Buffer0RtTag : in std_logic_vector(4 downto 0); Buffer1RtTag : in std_logic_vector(4 downto 0); Buffer2RtTag : in std_logic_vector(4 downto 0); Buffer3RtTag : in std_logic_vector(4 downto 0); Buffer0RdTag : in std_logic_vector(4 downto 0); Buffer1RdTag : in std_logic_vector(4 downto 0); Buffer2RdTag : in std_logic_vector(4 downto 0); Buffer3RdTag : in std_logic_vector(4 downto 0); -- output control signals - group 1 Sel0 : out std_logic; -- '1' indicates update from dispatch Flush : out std_logic_vector(3 downto 0); -- '1' indicates invalidate instruction valid bit Sel1Rs : out std_logic_vector(3 downto 0); -- '1' indicates update from cdb - highest priority Sel1Rt : out std_logic_vector(3 downto 0); -- '1' indicates update from cdb - highest priority En : out std_logic_vector(3 downto 0); -- '1' indicates update / shift OutSelect : out std_logic_vector(1 downto 0); -- goes to the big mux in front of CDB -- issue que unit control signals Issuequefull : out std_logic ; IssuequeReady : out std_logic ) ; end issuequectrl ; architecture behavctrl of issuequectrl is signal OutTemp : std_logic_vector ( 1 downto 0 ) ; signal OutSelectTemp , Entemp : std_logic_vector ( 3 downto 0 ) ;
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This note was uploaded on 09/26/2010 for the course EE 596 taught by Professor Antonioortega during the Fall '08 term at USC.

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issuequectrl - - CHECKED AND MODIFIED BY PRASANJEET...

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