issueque

issueque - - CHECKED AND MODIFIED BY PRASANJEET -UPDATED...

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-- CHECKED AND MODIFIED BY PRASANJEET ------------------------------------------- --UPDATED ON: 7/10/09 ------------------------------------------- ------------------------------------------------------------------------------- -- -- Design : Issue Queue -- Project : Tomasulo Processor -- Author : Rohit Goel -- Company : University of Southern California -- ------------------------------------------------------------------------------- -- -- File : issueque.vhd -- Version : 1.0 -- ------------------------------------------------------------------------------- -- -- Description : The issue queue stores instructions and dispatches instructions -- to the issue block as and when they are ready to be executed -- Higher priority is given to instructions which has been in the -- queue for the longes time ------------------------------------------------------------------------------- --library declaration library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; -- Entity declaration entity issueque is port ( -- Global Clk and Reset Signals clk : in std_logic ; reset : in std_logic ; -- Information to be captured from the CDB (Common Data Bus) CdbTag : in std_logic_vector(4 downto 0) ; CdbData : in std_logic_vector(31 downto 0) ; CdbValid : in std_logic ; -- Information from the Dispatch Unit IssuequeueEnable : in std_logic ; DisRsDataValid : in std_logic ; DisRtDataValid : in std_logic ; DisRdTag : in std_logic_vector ( 4 downto 0 ) ; DisRtTag : in std_logic_vector ( 4 downto 0 ) ; DisRsTag : in std_logic_vector ( 4 downto 0 ) ; DisRsData : in std_logic_vector ( 31 downto 0 ) ; DisRtData : in std_logic_vector ( 31 downto 0 ) ; DisOpcode : in std_logic_vector ( 2 downto 0 ) ; Issuequefull : out std_logic ; -- Interface with the Issue Unit Instready : out std_logic ; InstRsData : out std_logic_vector(31 downto 0) ; InstRtData : out std_logic_vector(31 downto 0) ;
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InstRdTag : out std_logic_vector(4 downto 0) ; InstOpcode : out std_logic_vector(2 downto 0) ; InstIssued : in std_logic ; -- Interface with ROB RobFlush : in std_logic; RobTopPointer : in std_logic_vector ( 4 downto 0 ) ; RobDepth : in std_logic_vector ( 4 downto 0 ) ) ; end issueque; -- Architecture architecture behav of issueque is -- Component declarations component issuequectrl port ( -- Global Clk and Reset Signals clk : in std_logic ; reset : in std_logic ; -- cdb interface CdbTag : in std_logic_vector(4 downto 0) ; CdbValid : in std_logic ; -- ROB Interface RobFlush : in std_logic ; RobTopPointer : in std_logic_vector (4 downto 0 ) ; RobDepth : in std_logic_vector (4 downto 0 ) ; -- dispatch / issue unit interface DisEnable : in std_logic ; IssueBlkDone : in std_logic ; -- shift register inputs InstructionValidBit : in std_logic_vector(3 downto 0); -- '1' indicates instruction is valid in the buffer RsDataValidBit : in std_logic_vector(3 downto 0); -- '1' indicates rs data is valid in the buffer RtDataValidBit : in std_logic_vector(3 downto 0); -- '1' indicates rt data is valid in the buffer
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issueque - - CHECKED AND MODIFIED BY PRASANJEET -UPDATED...

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