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Unformatted text preview: nMOS logic From Wikipedia, the free encyclopedia Jump to: navigation , search nMOS logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits . nMOS transistors have three modes of operation: cut-off, triode, and saturation (sometimes called active). The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output. As an example, here is a NOR gate in nMOS logic. If either input A or input B is high (logic 1, = True), the respective MOS transistor acts as a very low resistance between the output and the negative supply, forcing the output to be low (logic 0, = False). When both A and B are high, both transistors are conductive, creating the output to be low (logic 0, = False)....
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This note was uploaded on 09/29/2010 for the course GENERAL AR ECE 250 taught by Professor Drcapps during the Spring '10 term at N.C. State.
- Spring '10