lect23_notes - Foundations of Embedded Systems C Term...

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Unformatted text preview: Foundations of Embedded Systems C Term Spring 2009 Lecture #23: Interrupts and ISRs Reading for Today: User's Guide Ch 2, TI Mixed C language notes Reading for Next Class: Review all since Exam 2 HW #6 (on web): Due tomorrow! Lab #4 (on web): Report due Friday (3/6/09) EXAM #3 — Thursday 3/5/09 Last Class: One more procedure/stack example (lect21.s43) >> Using the Hardware Multiplier (meult.s43) Three (3) Ways to Alter Flow of Program Execution >> Jumps (BR) := (36%}, IIiP —> USe. for \oud C0n+ro\ o r i 00 P C V\ ‘3 >> Procedure CALLS = (Always) Go and RETurn (l? “we“ 615:0 5+ores Ve'l'urh q’c/C/VCSJ Ca.“ #SomeVunc J _ 0n 54ac/C m o v R l H , re s ’ >> Interrupts = External signals requesting CPU action >> Like procedures (labeled sub—blocks of code that execute and return) >> Request are initiated outside of CPU and tend to occur asynchronously >> Can be accepted and serviced by appropriate Interrupt Service Routine (ISR) -- Non—Maskable Interrupts (NMI) = Can not be disabled ’9 OSLRHA‘LN (Chem VQOH' —— Must be serviced (higher priorities) .— ~> ?OW€V raw H‘ —— Maskable interrupts can be disabled -- Must be individually enabled in order to be recognized and serviced Foundations of Embedded Systems A Term Fall 2008 Lecture #23: Interrupts and ISRs Reading for Today: User's Guide Ch 2, TI Mixed C language notes Reading for Next Class: Review all since Exam 2 HW #6 (on web): Due Monday 10/ 13/08 in class (BONUS!) Lab #4 (on web): Report due NEXT Thursday 10/ 16/08 EXAM #3 — Tuesday 10/14/08 Last Class: One more procedure/stack example(example code is posted) >> Using the Hardware Multiplier >> 3 ways to alter flow of program execution: jumps, procedure calls, interrupts. >> Interrupts are signals from peripherals requesting service from CPU. >> Sequence ovaent when an NMI or Enabled Interrupt Occurs... p ( 11) Any currently executing instruction rs completed. ,2.“ _.,__ __,_____.. 2. y They‘PE; which points to the next instruction, is pushed onto the stack. ‘y’ The SR is pushed onto the stack. Tne nterrupt with the highest priority is selected if multipée interrupts occurred during the last instruct on and are pending for service. 51v Tne interrupt request flag resets automatically on sihgieéource flags. Murtiple source flags remain set for servicing by software. “Mansfiwg 52A (Calais * < 3'1; ‘. Tne SR is cleared wrtn the excepteon o‘whtch is left unchanged. - V . . whee a; log K This terminates any low—power mode. Becuse the GE but is cleared. (.1 cur/L? for further intermgts are disabled ‘3 ‘ . . , ' DA 5 P use L 7.: The content of the interrupt vector :5 loaded into the PC: the program "4 continues wrth the interrupt service routine at that address. 2—6‘. interrupt Processmg Before After interrupt Interrupt >> Sequence of E vent when Returning from an Interrupt Return From Interrupt The .nterrupt handiing rc utine term mates thh the instruction: —-”"a-¢-. i RETI )1: return from an :nterrupt service routine) The return from the interrupt takes 5 cycies to execute the fol-icwing actions and is a iiustrated in Figure" ‘- <~J 1D:h he SR with all prevaous settxn s o s from the stack. All prewcus settings GIE. CPUOFF etc. are now an effect regardiess cf the settings used during the Interrupt service routine w (9 '_"he PC 5 fwm the stack and begins execution at the point where it was interru ted figure 2— .7. Return From interrupt Before After Return From interrupt Ins.<}.€ I3 ‘2 Intermpt nesting is enabled ff the GE bit is set inside an interrupt service routine. When Interrupt nesting is enabied. any interrupt occurring during an interrupt service routine wifl nterrupt the routine. regardless of the interrupt priorities ~-~—-——>§‘\o..; L ”Pm yam Zaecu‘rwm CWMLM / -....~+______&:1;»~__+_____“ . - INYb \ ~: ,Itfiquwgate Cum ocgui" at an!) ‘hme c’urms . .. . . ~ ~4ixew+ion z.» AD YNCH mews] 19W ‘Mf L3 ”GEL/CL \1 .H V'\ ., I: -\ at e A k L C Ox [\L \ (KC aw What if multiple interrupts occur? >> REMEMBER: By default all interrupts are disabled inside an ISR because status register (SR) is cleared ——> Programmer (i.e. YOU) must re—enable interrupts inside ISR for multiple interrupts to be acknowledged. Otherwise, additional interrupts are ignored while inside ISR \ W >> RETI restores the SR and will re-enable interrupts automatically at end of ISR Ekampk: ; Inside main MOV @R7, R4 ; INT from ADC occurs ADC_isr ; ISR for A—to—D converter EINT ; re—enable interrupts inside ISR PUSH R6 PUSH R8 ; INT from TIMERB occurs and is serviced POP R8 POP R6 RETI TB_ISR ; ISR for Timer B PUSH R5 ; preserve R5 INC &TB_cnt ; another INT occurs but is ignored because interrupts were not re—enabled within this ISR ‘0 ‘0 POP R5 RETI 3%) film/,3 tn‘lerrvP‘i \HVC‘ OCCU‘QS’ LJHAQ r:'\i€3t\lu‘3)+> (My Cfiisalffléc—l ‘3 sT‘t‘s a“: to ‘IMTEAIZ‘RUPT SOQRLE +0 .21: ‘ny K“ 5’ K) E Vi (ft/ck‘i *6 L. H + Qv’Y‘up + t a 2:?) t "W t 7 “l i» v. on Q :5 L r’\ “i l 3» S L M l3 I) (j / MSP430F449 -- Interrupt Vector Addresses and Priorities ‘ Vector Address Priority f Interrupt Source I OxFFFE 15 (highest) Hard RESET (POR) 33 , OxFFFC 14 = NMI(osci11ator/flash/user nmi) )k I OXFFFA 13 TimerB T OXFFFS 12 Timer B OxFFF6 V ll Compatitor 0xFFF4 ‘ 10 WDT ' H OxFFFZ 9 USARTO Rx 7 OxFFFO 8 USARTO Tx T OxFFEE 7 ADC fi—(lidgFEC 6 Timer A ‘ OXFFEA- 5 TimerA r7 0xFFE8 4 Portl i I OxFFE6 3 USARTl Rx 0xFFE4 iiiiii 2 USARTl Tx 0xFFE2 1 : Port 2 OXFFEO 0 (lowest) 3 Basic Timer ”a ,4" L:> RESET and NMI can not be ignored! 93146 its because ‘H‘Qts are ("‘é' \ngQA *0 C andti‘wwxs "\__ O '0 O-ZW Interrupts are an example of “double indirection” timed PM; we. v\+ \ V \ operwl'toA (V3 M5 PAS 0 >> In high level programming this would be equivalent to a “pointer to a pointer” >> The CPU knows what INTERRUPT VECTOR address between OxFFEO and OxFFFE is associated with each interrupt source (see table above) "9‘1’kt3 CLSSlCO’flfli‘lévl'l' 5,: addresses is Can: D >> In the MSP430, when an interrupt is received from a particular source (and interrupts are enabled) the CPU gets the address (label) of the Interrupt Service Routine (ISR) stored in the Interrupt Vector table automatically >> BUT, assembly programmer must place address of ISR in Interrupt Vector Table ORG OxFFEZ ; Interrupt Vector Address for Port 2 , dw port2__ISR ; Label (address) of Port 2 ISR is stored, h e r e <\ >> Also, programmer (C or assembly) must implement the interrupt service routine I? v) 1:: Mxmfi 15PUWP05€ Cali‘fl flared in {n‘l‘ VGLlOV’TQLJ‘e ‘4?le On Lm'le’Yfl/‘Pt pfoéjracvw UJ‘ H .3 UMP *0 echct'i' Ever" 1-3031); q_éére$5 l5 +h€rfll port2_ISR ; syntax similar to a procedure W69 x A“ N3 ; ISR performs a SMALL function to 'V‘D( vDQ}Qb ; ”answer request” from interrupt source ‘0 V6 ; That's it ‘V‘Ob RETI ; must end with RETI $503+ 80\V€ whole ”Pp tinsLJe 15/?! Flow of Program Execution and the Stack when Interrupts Occurs ; Somewhere in a Main Loop MOV OXOAOO, SP EINT ; enable interrupts MOV R7, R12 MOV &var2, R14 ‘ CALL #someProc I ca.“ armceéure J MOV R12, result someProc ; this procedure does something PUSH R5 ; preserve R5 ADD R5, R14 DEC R5 ; **Interrupt occurs from Port2 TST R5 POP R5 RET What will the stack loop like as this code executes? lb b“.+ womb —>Li++le Enam (LOU; BfiTe in Low ev' “i‘iADStCKC. \< cu wag) Stages, addrefisx STACK Address 2 Contents 0 (L T OXOAOO —- <» 1? i . , l tOxO9FF :95 mm (M: R ~ 20x09FE pg m mzCLe 3k , ' 190? RS OxO9FD RS (“[3 0x09FC E5 Lu) 4 0xO9FB ‘ PC ‘54; (3,“) .0x09FA ' " ' , 0x09F9 SK QM 0x09F8 1 52 up) OXO9F7 i0x09F6 0x09F5 | Ex: Consider monitoring for Button Press. On the interface board we use in lab, the buttons are connected to Port 3 pins 7-4. Port 3 is not capable pf generating interrupts. For this example only, we will assume that we have 1 button connected to Port 2 pin 7. The program measures how quickly the user responds (by pressing the button) to some event like an LED flash. Configuring the digital I/O port for the button (in C) stEL &= ~BIT7; // select P2.7 for digital I/O ” y ,3 P2DIR &= ~BIT7; // make P2.7 and input [x “(Rest In assembly AND #7F, P2DIR // select P2.7 for digital I/O 3 a/ waM AND #7F, PZSEL // make P2.7 and input > Also need to configure and enable interrupt associated w/ Port2 __m>~, \5», Vic“? MT! 5 93 \~¥i’\€(C l5) (L var \ocb le l I’x \7 (4 iE-A b: r"\ Aria Aji \ 1") S (2. ‘i‘ +0 @ bC ngré ‘ .‘ . A 13+ \ ‘ iv tic \ 'lfiregsegi (dincl “HEW” ""‘ b «VA», 5 ;&;y\ » U V l \ b 1.— . + ‘ 1 a. \ e A f {all e- \ cg: e. LL) (er4 \l a 3 <2, \Dtv’x mm i, + 2 What makes a GOOD Interrupt Service Routine? >> Preserve CPU registers! (Done Automatically in C but MUST be done by programmer in assembly) >> Service the device as efficiently as possible >> Restore registers >> RETI That's it! Guidelines to remember... >> DON'T solve WHOLE APPLICATION in ISR >> All ISR’s are too long!!! Initializing Interrupt Vector Table in Assembly and in C (v— Habit“ >> Only initialize interrupts that are necessary and locally germane mwh%3i““*=hwqumIm,_I :5 3+1: , 0 ,C Ofl‘p\50v‘e I A‘hflv‘ruer Evfint \,,,,,, Q (P A ,7, Irfi‘firfllp'l ,, . , In4€rrup,i,..Ek-20do)£. , ' wQ, QQA-k +O CausQ ‘er .>3u++oa m”; if 4 C3 Jpresse ,, L, LO,6],C,,,, ,+,Q, 4 causes , L031; Q ,7L,\,(,6Ln51,+‘lo,v\ ,,,,, P36 B Pam Pg. E) , 3) ,bfiflQYGk\ InwlerruPJr rEnCLbJ‘Q ENVTqu$%£”@2%LZL”I“I >> BUT “As goes one so go us all” If you enable 1 interrupt then you SHOULD provide interrupt vectors for ALL! (why 7) ——> Can send all unused interrupts to same Invalid_Interrupt handler invalid_isr: ; handles erroneous or spurious interrupts RETI Syntax for Interrupts in ms2430 Assembly // Write address of ISR at proper place in Interrupt Vector Table ORG OxFFEZ ; Interrupt Vector Address for Port 2 dw port2_ISR ; Label (address) of Port 2 ISR // Then, implement the interrupt service routine assigning it the same label name port2_ISR ; syntax similar to a procedure ; ISR performs a SMALL function to ; “answer request" from interrupt source ; That's it RETI ; must end with RETI Also Rcall Syntax for Interrupts in C // Define an interrupt service routine using #pragma / / #pragma vector = name of interrupt vector from msp430x4xx.h #pragma vector=PORT2_VECTOR __interrupt void port2isr(void) { // implement ISR in C // } // Global Interrupt enable —— near beginning of main _BIS_SR(GIE); _EINT(); // can be used to enable or disable _DINT(); // interrupts within C code Fil /* ** 7* ,. H /* 13 /* . /* #i mam. _ W‘x / ’A\ W\_ e: /home/sjarvis/ece280l_AO7/buttonlNT.s43 *********X*********************************** This code lightsan LED then makes a measurement of the time until a button assumed to be on Port 2 Pin 7 is pressed *********X***********************************/ \ ~,, “/- * NQIE: This is just an example. The code will * not run on our lab MSP430 boards because * Port 2 pin 7 is not connected to a button! A/ nclude "msp430x44x.h" **/ **/ §é **/ // Assembler directive instruct the assembler program // as to how certain memory locations should be initialized. // Assembler directives are only ”run” when IAR downloads // code to the chip. They are NEVER executed by the CPU. I ;S cn bt NAME buttonExample ; name of program PUBLIC main ; make main visible ORG OxFFFE ; setup RESET vector to go to dw main ; the address labeled main ORG 0xFFE2 ; setup the port 2 interrupt vector dw port2_ISR ; with address of ISR ; SHOULD set all unused interrupt vectors to go to <f,/;;’ invalidISR. I show only one example here ORG 0xFFEE ; setup the ADC interrupt vector dw invalidISR ; to go to invalidISR 9192....21511913 imam 'T‘ ORG 0200h ; beginning at address 200h t d532 1 ; allocate space for one 32-bit word n d58 1 ; allocate space for one byte ma to RSEG CODE ; define a relocatable code 5 in MOV #0A00h, SP ; initialize SP to top CALL #configLED ; procedure to setup LE CALL #configBTN ; procedure to setup Bu CALL #configBTN_int ; enable interrupts CALL #LEDoff ; start with LED off EINT ; general interrupt ena p MOV #cnt, R10 ; put address of cnt (20 ; the next 2 instructions set cnt = @000 CLR @R10+ ; clear the word whose ad ; then increment R10 = R1 CLR @R10 ; clear the word whose ad CLR.B btn ; byte labeled btn = 0 CALL #delay procedure for SW delay CALL #LEDon ' turn on LED MOV #cnt, R10 ; put address of cnt (20 ; the next 2 instructions increment 32-bi INC @R10+ ; Increment word whose ad ; then increment R10 = R1 egment of RAM D tton for Button ble 0h) in R10 0000h dress is in R10 0+2 dress is in R10 0h) in R10 t cnt dress is in R10 0+2 Page 1 of 2 INN C6L$€i ‘b)e SyflJf dkh errors eous é nierrupf same how] File: /home/sjarvis/ece280l_A07/button|NT.s43 Page 2 of 2 ADC @RlO ; add the carry bit to high word of cnt TST B btn ; check if btn = 0 J2 lp ; Jump on zero back to lp as ; button hasn't been pressed yet ; Otherwise btn has been pressed CALL #LEDoff ; turn off LED CALL #delay ; wait a while JMP top ; forever loop back to top port2_ISR; Assumes only pin 7 has interrupt enabled MOV.B #Olh,btn ; just update button status RETI invalidISR; If receive spurrious interrupt just return RETI configBTN; PUSH R4 preserve R4 MOV B #80h, R4 set bit 7 INV R4 NOT(R4) AND.B R4,P25EL AND B R4,P2DIR POP R4 RET PZSEL = PZSEL & ~BIT7 PZDIR = P2DIR & ~BIT7 restore R4 configBTN_int; BIS.B #80h,P21ES ; interrupt on 1 to 0 transition BIS.B #80h,PZIE ; enable port2 pin 7 interrupt RET ; LED procedures and delay procedure not implememnted... ...
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