Lec-11-Comp-Arch-2-22-10(2)

Lec-11-Comp-Arch-2-22-10(2) - IA-32 Architecture Ratan...

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Unformatted text preview: IA-32 Architecture Ratan GuhaCIS 3360, Spring 2010February 22, 20101Lecture IA-32 Architecture2Resources UsedReferences: Kip Irvine – Assembly Language for Intel-Based Computers, Prentice Hall, 2007, (ISBN 0-13-238310-1)Intel – Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic ArchitectureSome of the slides are taken from the slides prepared by the author Kip Irvine for the book Assembly Language for Intel-Based Computers, Prentice Hall, 2007Some of the slides are taken from InternetLecture IA-32 ArchitectureOverviewGeneral ConceptsIA-32 Processor ArchitectureSample Assembly Language ProgramComponents of an IA-32 MicrocomputerInput-Output System3Lecture IA-32 ArchitectureGeneral ConceptsBasic microcomputer designInstruction execution cycleReading from memoryHow programs run4Lecture IA-32 ArchitectureBasic Microcomputer Designclock synchronizes CPU operationscontrol unit (CU) coordinates sequence of execution stepsALU performs arithmetic and bitwise processing5Lecture IA-32 ArchitectureBasic instructionsData transferControl transferStack manipulationArithmetic operatorsLogical operators6Lecture IA-32 ArchitectureClocksynchronizes all CPU and BUS operationsmachine (clock) cycle measures time of a single operationclock is used to trigger eventsone cycle17Lecture IA-32 ArchitectureInstruction Execution CycleFetchDecodeFetch operandsExecute Store output8Lecture IA-32 ArchitectureReading from MemoryMultiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are:❍address placed on address bus❍Read Line (RD) set low❍CPU waits one cycle for memory to respond❍Read Line (RD) goes to 1, indicating that the data is on the data busCycle 1Cycle 2Cycle 3Cycle 4DataAddressCLKADDRRDDATA9Lecture IA-32 ArchitectureCache MemoryHigh-speed expensive static RAM both inside and outside the CPU.❍Level-1 cache: inside the CPU❍Level-2 cache: outside the CPUCache hit: when data to be read is already in cache memoryCache miss: when data to be read is not in cache memory.10Lecture IA-32 ArchitectureCISC and RISCCISC – complex instruction set❍large instruction set❍high-level operations❍requires microcode interpreter❍examples: Intel 80x86 familyRISC – reduced instruction set❍simple, atomic instructions❍small instruction set❍directly executed by hardware❍examples: •ARM (Advanced RISC Machines)•DEC Alpha (now Compaq)11Lecture IA-32 ArchitectureIntel Microprocessor HistoryIntel 8086, 80286IA-32 processor familyP6 processor family12Lecture IA-32 ArchitectureEarly Intel MicroprocessorsIntel 8080 (1974)❍64K addressable RAM❍8-bit registers❍CP/M operating system❍S-100 BUS architecture❍8-inch floppy disks!...
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This note was uploaded on 10/05/2010 for the course CIS CIS 3360 taught by Professor Guha during the Spring '10 term at University of Central Florida.

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Lec-11-Comp-Arch-2-22-10(2) - IA-32 Architecture Ratan...

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