Lec-11-Comp-Arch-2-22-10(2) - IA-32 Architecture Ratan Guha...

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IA-32 Architecture Ratan Guha CIS 3360, Spring 2010 February 22, 2010 1 Lecture IA-32 Architecture
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2 Resources Used References: Kip Irvine– Assembly Languagefor Intel-Based Computers, PrenticeHall, 2007, (ISBN 0-13-238310-1) Intel – Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture Someof theslides aretaken from theslides prepared by theauthor Kip Irvinefor thebook Assembly Languagefor Intel-Based Computers, PrenticeHall, 2007 Someof theslides aretaken from Internet Lecture IA-32 Architecture
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Overview General Concepts IA-32 Processor Architecture Sample Assembly Language Program Components of an IA-32 Microcomputer Input-Output System 3 Lecture IA-32 Architecture
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General Concepts Basic microcomputer design Instruction execution cycle Reading frommemory How programs run 4 Lecture IA-32 Architecture
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Basic Microcomputer Design clock synchronizes CPU operations control unit (CU) coordinates sequenceof execution steps ALU performs arithmetic and bitwiseprocessing 5 Lecture IA-32 Architecture
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Basic instructions Data transfer Control transfer Stack manipulation Arithmetic operators Logical operators 6 Lecture IA-32 Architecture
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Clock synchronizes all CPU and BUS operations machine(clock) cyclemeasures timeof a singleoperation clock is used to trigger events one cycle 1 0 7 Lecture IA-32 Architecture
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Instruction Execution Cycle Fetch Decode Fetch operands Execute Storeoutput 8 Lecture IA-32 Architecture
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Reading from Memory Multiplemachine cycles are required when reading from memory, because it responds much more slowly than the CPU. Thesteps are: address placed on address bus Read Line(RD) set low CPU waits onecyclefor memory to respond Read Line(RD) goes to 1, indicating that thedata is on thedata bus Cycle 1 Cycle 2 Cycle 3 Cycle 4 Data Address CLK ADDR RD DATA 9 Lecture IA-32 Architecture
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CacheMemory High-speed expensivestatic RAM both insideand outside theCPU. Level-1 cache: insidethe CPU Level-2 cache: outsidetheCPU Cachehit: when data to beread is already in cache memory Cachemiss: when data to beread is not in cachememory. 10 Lecture IA-32 Architecture
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CISC and RISC CISC – complex instruction set largeinstruction set high-level operations requires microcodeinterpreter examples: Intel 80x86 family RISC – reduced instruction set simple, atomic instructions small instruction set directly executed by hardware examples: ARM (Advanced RISC Machines) DEC Alpha (now Compaq) 11 Lecture IA-32 Architecture
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Intel Microprocessor History Intel 8086, 80286 IA-32 processor family P6 processor family 12 Lecture IA-32 Architecture
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Early Intel Microprocessors Intel 8080 (1974) 64K addressableRAM 8-bit registers CP/M operating system S-100 BUS architecture 8-inch floppy disks!
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