cs8803SC_lecture9 - 1 CS8803SC Software and Hardware...

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Unformatted text preview: 1 CS8803SC Software and Hardware Cooperative Computing Review computer architecture topics Prof. Hyesoon Kim School of Computer Science Georgia Institute of Technology Thinking Parallel Histogram Sequential code for (int i = 0; i < BIN_COUNT; i++) Result[i] = 0; for (int i = 0; i < dataN; i++) { Result[data[i]]++; } With CUDA? 2 4 6 8 10 12 1 2 3 4 5 6 7 8 9 10 2 Review Computer Architecture Topics Pipeline OOO processors MT/SMT DRAM Interleaved memory Prefetcher 0x0002 0x0003 Overview of a Processor PC WB I-$ D-$ RF LD R1, MEM[R0] ADD R2, R2, #1 BR ZERO 0x0001 0x0001 0x0002 0x0003 0x0001 15 cycles 7 cycles DEC Non-pipelined Pipelined 0x0002 0x0003 t 3 Out of order Processor (ooo) PC WB I-$ D-$ Rename DEC Scheduling Window Fetch->Decode->Rename->Scheduling->Execution->Retire issue dispatch Company 1 dispatch issue Company 2 G80 architecture? Superscalar pipeline Complex-effective superscalar processors, Palacharla, Jouppi, and Smith 4 MT HEP (Heterogeneous Element Processor) (78~85) The first commercial system designed to apply multiple processors to a single computation, and the first to have multithreaded CPUs 1 wide issue, in-order machine Up to 128 active contexts 8 pipeline stages Always fetch from different threads...
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This note was uploaded on 10/06/2010 for the course CS 8803 taught by Professor Staff during the Spring '08 term at Georgia Institute of Technology.

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cs8803SC_lecture9 - 1 CS8803SC Software and Hardware...

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