hw4 - EE114 Autumn 09/10 R. Dutton Page 1 of 3 HOMEWORK #4...

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EE114 Autumn 09/10 R. Dutton Page 1 of 3 HOMEWORK #4 (Due: Friday, October 23, 2009, noon PT) 1. Consider the cascode circuit (CS-CG) on slide 24 of lecture 10 but with modified bias conditions (I B given below, assume zero current through R). For simplicity in this problem assume =0 and ignore backgate effect in your calculations. a) Calculate the quiescent point voltage at the source of MNC (V X ) for the case that I B is such so as to keep both the devices in saturation and V O =V B =2.5V. Assume all other parameters in the circuit are the same. b) Compute all intrinsic and extrinsic device capacitances of MN1 and MNC. For the calculation of junction capacitances, use your result from part (a) and assume V O =V B =2.5V (make sure for your simulations that V I gives you this value as well). c) Compute the -3dB bandwidth of this circuit using a ZVTC analysis. How closely does your answer match your simulation result? State the percent error. d) Compare the symbolic expression for the time constant associated with C gd of MN1 in this circuit with the expression on slide 10 of lecture 9. Explain qualitatively why the cascode helps improve the -3dB bandwidth in this circuit. 2. In this problem, we will investigate an interesting case in which the benefit of cascoding is dependent upon operating frequency. In the cascoded common source stage shown in Figure
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hw4 - EE114 Autumn 09/10 R. Dutton Page 1 of 3 HOMEWORK #4...

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