paper4 - System-in-Package Design and Test Electronic...

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System-in-Package Design and Test 220 0740-7475/06/$20.00 © 2006 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers SYSTEM-ON-CHIP (SoC), system-on-package (SoP), and system-in-package (SiP) technologies promise efFcient, cost-effective, and powerful pathways for realizing complex electronic products. Much of this promise is unrealized owing to a lack of a comprehensive design methodology and supporting tools at the conceptual and speciFcation levels, the early and detailed design levels, and the integra- tion and test levels. The failure to develop such tools stems from the new computation models required for specifying multicore heterogeneous systems and the inability to code- sign and test multidomain (analog, digital, R±, and opto- electronic) subsystems concurrently and iteratively. ±urther contributing to the problem is the lack of a synthesis capa- bility for products’ nondigital functions. Although well understood, this problem won’t be solved soon, because it involves nearly a dozen areas of design expertise for which designers have few automation tools and even less under- standing of their interdependencies. Current electronic system design-and-test method- ologies for communications, wireless, and computing applications can beneFt from a migration to a platform- centric approach, which decouples early design from detailed design of product platforms. This methodology maps systems to prefabricated platforms (representing generic templates for implementing domain-speciFc products), which designers then customize to derive new products efFciently, correctly, and quickly. This platform- centric methodology partitions the design-and-test process into three tasks: representing the speciFcation, selecting and customizing a platform into a product, and creating library platform objects. Such an approach isolates the experimental nature of platform library creation from in-cycle design tasks. The problem New capabilities defining modern packaging have influenced all aspects of the electronic-product design process, changing the way the design is specified, partitioned, implemented, and tested. Designing an electronic pack- age is no longer relegated to the last stages of the design process, prior to integration and test. ±or instance, as recent product releases by major desktop vendors demonstrate, the change to multicore design affects the application’s functional representation (and its under- lying computation model) as integrated in the product. Nonetheless, with all the advances in packaging and SoC technologies, design and test has not advanced com- mensurately. CospeciFcation, codesign, cosimulation, and cosynthesis of digital, analog, R±, optoelectronic, soft- ware, and passive functionality are proving to be very difFcult problems. The conceptual challenge to imple- menting efFcient design methodologies is that digital designs can be synthesized from high-level speciFcations (for example, from behavior to geometry), whereas most R± and analog designs must be synthesized in the reverse order (from geometry to behavior). ±urthermore, code-
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paper4 - System-in-Package Design and Test Electronic...

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