COS226 - Lecture - Shared Memory - 1

COS226 - Lecture - Shared Memory - 1 - COS226: Concurrent...

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COS226: Concurrent Systems Chapter 4: Shared Memory – Part 1
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Sequential Parallel Safety (consistency) Liveness (progress) Quiescent Sequential Linearization wait-free lock-free Programs
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Registers (Visualized) public interface Register<T> { T read(); void write(T v); }
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Registers (Visualized) public class SequentialRegister<T> implements Resiter<T> { private T value; public T read() { return value; } public void write(T v) { value = v; } }
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Registers (Investigated) Registers are primitives; Can not make use of mutual exclusion to describe registers; Instead, make use of progress properties; Complexity is determined by the numbers of readers and writers; Therefore, wait-free registers.
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Registers (Investigated) Different registers provide different guarantees; Registers differ by: Values supported (boolean, M-valued integers); Numbers of readers/writers; Type of consistency provided.
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Safe Registers A MRSW register implementation is safe if: a read() call that does not overlap a write() call
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This note was uploaded on 10/11/2010 for the course COS COS226 taught by Professor Klazar during the Spring '10 term at University of Pretoria.

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COS226 - Lecture - Shared Memory - 1 - COS226: Concurrent...

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