cse331-week6new

cse331-week6new - CSE 331 Computer Organization and Design...

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CSE331 W06.1 KB Spring 2007 PSU CSE 331 Computer Organization and Design Spring 2010 Week 6 Course material on ANGEL: cms.psu.edu [ Thanks to Mary Jane Irwin adapted from D. Patterson slides]
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CSE331 W06.2 KB Spring 2007 PSU Head’s Up Last week’s material Assemblers, linkers and loaders Exam 1 on Feb 15 Monday, Hosler 26, 6:30 to 7:45pm This week’s material VHDL - Reading assignment –Y Chp1-5, PH B.4 Next week’s material MIPS arithmetic and ALU design - Reading assignment – PH 3.1-3.5, B.5-B.6 Reminders Exam #2 is Wed, March 31, 6:30 to 7:45pm, Hosler 26
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CSE331 W06.3 KB Spring 2007 PSU Processor Organization Processor control needs to have the Ability to input instructions from memory Logic to control instruction sequencing and to issue signals that control the way information flows between the datapath components and the operations performed by them Processor datapath needs to have the Ability to load data from and store data to memory Interconnected components - functional units (e.g., ALU) and storage units (e.g., Register File) - for executing the ISA Need a way to describe the organization High level (block diagram) description Schematic (gate level) description Textural (simulation/synthesis level) description
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CSE331 W06.4 KB Spring 2007 PSU Why Simulate First? Physical breadboarding (as in CSE 275) discrete components/lower scale integration precedes actual construction of the prototype verification of the initial design No longer possible as designs reach higher levels of integration! Simulation before construction - aka functional verification high level constructs means faster to design and test can play “what if” more easily limited performance (can’t usually simulate all possible input transitions) and limited accuracy (can’t usually model wiring delays accurately)
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CSE331 W06.5 KB Spring 2007 PSU Levels of Digital System Description Architectural Functional(Behavioral) Register Transfer Logic Circuit model is a high level view written in a programming language model is a block diagram view model is in terms of datapath FUs, registers, busses; register xfer operations are clock phase accurate model is in terms of logic gates; delay information can be specified for gates; digital waveforms model is in terms of circuits (electrical behavior); accurate analog waveforms Less Abstract More Accurate Slower Simulation Special languages + simulation systems for describing the inherent parallel activity in hardware ( VHDL and verilog) Schematic capture + logic simulation package like LogicWorks
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CSE331 W06.6 KB Spring 2007 PSU In some form, nearly all design activities of a microprocessor development are aimed at getting the SRTL [structural RTL] model right. We started writing a C program to model the essentials
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cse331-week6new - CSE 331 Computer Organization and Design...

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