cse331-week14sp10 - CSE 331 Computer Organization and...

Info icon This preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
CSE331 W14.1 KB Fall 2008 PSU CSE 331 Computer Organization and Design SPRING 2010 Week 14 Section 1&2: Kabekode V Bhat Course material on ANGEL: cms.psu.edu [ Thanks to Mary Jane Irwin adapted from D. Patterson slides]
Image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
CSE331 W14.2 KB Fall 2008 PSU Head’s Up Last week’s material Input/Output – dealing with exceptions and interrupts This week’s material Intro to pipelined datapath design; memory design - Reading assignment – PH: 6.1, B.9 Next week’s material Memory hierarchies - Reading assignment – PH: 7.1-7.2 Reminders CMPEN331 FINAL EXAM Filing grade corrections/updates-Deadline Week before Final
Image of page 2
CSE331 W14.3 KB Fall 2008 PSU We knew from the beginning that deciding on an out- of-order microarchitecture was the number one conceptual priority … An out-of-order core would imply a much more complicated engine, which would tend to increase the number of pipeline stages, which would impact the clock frequency (making it either higher or lower, we were not entirely sure which). The Pentium Chronicles , Colwell, pg. 20
Image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
CSE331 W14.4 KB Fall 2008 PSU Review: Single Cycle vs. Multiple Cycle Timing Clk Cycle 1 Multiple Cycle Implementation: IFetch Dec Exec Mem WB Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 IFetch Dec Exec Mem lw sw IFetch R-type Clk Single Cycle Implementation: lw sw Waste Cycle 1 Cycle 2 multicycle clock slower than 1/5 th of single cycle clock due to stage register overhead
Image of page 4
CSE331 W14.5 KB Fall 2008 PSU How Can We Make It Even Faster? Split the multiple instruction cycle into smaller and smaller steps There is a point of diminishing returns where as much time is spent loading the state registers as doing the work Start fetching and executing the next instruction before the current one has completed Pipelining – (all?) modern processors are pipelined for performance Fetch (and execute) more than one instruction at a time (out-of-order superscalar and very long instruction word (VLIW) (epic) – CSE 431) Fetch (& execute) instructions from multiple instruction stream: multi(hyper threading) – CSE 431
Image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
CSE331 W14.6 KB Fall 2008 PSU A Pipelined MIPS Processor Start the next instruction before the current one has completed improves throughput - total amount of work done in a given time instruction latency (execution time, delay time, response time - time from the start of an instruction to its completion) is not reduced Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 IFetch Dec Exec Mem WB lw Cycle 7 Cycle 6 Cycle 8 sw IFetch Dec Exec Mem WB R-type IFetch Dec Exec Mem WB - clock cycle (pipeline stage time) is limited by the slowest stage - for some instructions, some stages are wasted cycles
Image of page 6
CSE331 W14.7 KB Fall 2008 PSU Single Cycle, Multiple Cycle, vs. Pipeline Multiple Cycle Implementation: Clk Cycle 1 IFetch Dec Exec Mem WB Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 IFetch Dec Exec Mem lw sw IFetch R-type lw IFetch Dec Exec Mem WB Pipeline Implementation: IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem WB R-type Clk Single Cycle Implementation: lw sw Waste Cycle 1 Cycle 2
Image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 8
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern