cse331-week14sp10

cse331-week14sp10 - CSE 331 Computer Organization and...

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CSE331 W14.1 KB Fall 2008 PSU CSE 331 Computer Organization and Design SPRING 2010 Week 14 Course material on ANGEL: cms.psu.edu [ Thanks to Mary Jane Irwin adapted from D. Patterson slides]
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CSE331 W14.2 KB Fall 2008 PSU Head’s Up Last week’s material Input/Output – dealing with exceptions and interrupts This week’s material Intro to pipelined datapath design; memory design - Reading assignment – PH: 6.1, B.9 Next week’s material Memory hierarchies - Reading assignment – PH: 7.1-7.2 Reminders CMPEN331 FINAL EXAM Filing grade corrections/updates-Deadline Week before Final
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CSE331 W14.3 KB Fall 2008 PSU We knew from the beginning that deciding on an out- of-order microarchitecture was the number one conceptual priority … An out-of-order core would imply a much more complicated engine, which would tend to increase the number of pipeline stages, which would impact the clock frequency (making it either higher or lower, we were not entirely sure which). The Pentium Chronicles , Colwell, pg. 20
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CSE331 W14.4 KB Fall 2008 PSU Review: Single Cycle vs. Multiple Cycle Timing Clk Cycle 1 Multiple Cycle Implementation: IFetch Dec Exec Mem WB Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 IFetch Dec Exec Mem lw sw IFetch R-type Clk Single Cycle Implementation: lw sw Waste Cycle 1 Cycle 2 multicycle clock slower than 1/5 th of single cycle clock due to stage register overhead
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CSE331 W14.5 KB Fall 2008 PSU How Can We Make It Even Faster? Split the multiple instruction cycle into smaller and smaller steps There is a point of diminishing returns where as much time is spent loading the state registers as doing the work Start fetching and executing the next instruction before the current one has completed Pipelining – (all?) modern processors are pipelined for performance Fetch (and execute) more than one instruction at a time (out-of-order superscalar and very long instruction word (VLIW) (epic) – CSE 431) Fetch (& execute) instructions from multiple instruction stream: multi(hyper threading) – CSE 431
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CSE331 W14.6 KB Fall 2008 PSU A Pipelined MIPS Processor Start the next instruction before the current one has completed improves throughput - total amount of work done in a given time instruction latency (execution time, delay time, response time - time from the start of an instruction to its completion) is not reduced Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 IFetch Dec Exec Mem WB lw Cycle 7 Cycle 6 Cycle 8 sw IFetch Dec Exec Mem WB R-type IFetch Dec Exec Mem WB - clock cycle (pipeline stage time) is limited by the slowest stage - for some instructions, some stages are wasted cycles
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CSE331 W14.7 KB Fall 2008 PSU Single Cycle, Multiple Cycle, vs. Pipeline Multiple Cycle Implementation: Clk Cycle 1 IFetch Dec Exec Mem WB Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 IFetch Dec Exec Mem lw sw IFetch R-type
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This note was uploaded on 10/12/2010 for the course CMPEN 331 taught by Professor Bhat during the Spring '08 term at Penn State.

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cse331-week14sp10 - CSE 331 Computer Organization and...

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